PCB Manufacturer & PCB Assembly

Two Ways to Create Blind and Buried Vias in Cadence Allegro

Posted on April 27, 2026 by NextPCB Content Team

Learn two efficient methods to create blind and buried vias in Cadence Allegro, with step-by-step setup for HDI PCB stackups and design tips.

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Tag: PCB design Blind & Buried Vias pcb layout HDI PCB blind vias PCB Stackup Pad Design Cadence Allegro

How to Add and Plan Multi-layer PCB Stackups in Altium Designer?

Posted on May 08, 2026 by NextPCB Content Team

Learn how to scientifically plan multilayer PCB stackups in Altium Designer to control impedance and crosstalk, featuring practical tips and common FAQs.

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Tag: PCB design pcb design software Altium designer EDA Hardware Engineer signal integrity (SI) PCB Stackup

Choosing the Right Substrate Materials for PCB Manufacturing: A Comprehensive Guide

Posted on March 20, 2026 by NextPCB Content Team - PF

The PCB substrate, professionally known as copper clad laminate, forms the base of every PCB. Understanding how to select the right substrate material is essential for ensuring your PCB performs reliably under real-world conditions.

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Tag: MCPCB CTE Flexible PCBs High-TG PCBs PCB manufacturing FR4 hardware design Rogers PCB electronics engineering pcb substrates

Bulk Capacitor vs Decoupling Capacitor: Understanding the Three-Tier Capacitor Strategy

Posted on June 15, 2026 by Stacy Lu

Learn the key differences between bulk and decoupling capacitors. Discover the three-tier capacitor strategy for power integrity in high-speed PCB layouts.

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ESR and ESL in Capacitors: What They Mean and Why They Matter in PCB Power Integrity

Posted on June 15, 2026 by Stacy Lu

Discover what ESR and ESL in capacitors mean for your PCB design. Learn how equivalent series resistance and inductance impact power integrity and component layout.

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X7R vs C0G vs X5R: MLCC Dielectric Types Explained for PCB Engineers

Posted on June 15, 2026 by Stacy Lu

Discover the differences between X7R, C0G (NP0), and X5R MLCC dielectrics. Learn how temperature coefficients and DC bias impact your PCB design.

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Tag: Arduino

Decoupling Capacitor Placement: Rules & Strategies for High-Speed PCB

Posted on June 15, 2026 by Stacy Lu

Decoupling capacitor placement guide for PCB engineers—three-tier strategy, value selection, distance rules, via placement, power plane interaction, and common layout mistakes to avoid.

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Accelerator PCB PDN Design: VRM & Decoupling Guide

Posted on June 12, 2026 by Stacy Lu

Deep technical guide on Power Delivery Network (PDN) design for AI accelerator cards. Explore VRM design, decoupling capacitor optimization, and PDN analysis.

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Tag: NextPCB PCB Design & Layout AI High-Speed PCB Design PCB capacitors PDN

AI Accelerator PCB Design Guide: Layers, Materials and Signal Integrity for H100/H200 Boards

Posted on June 04, 2026 by Stacy Lu

Master AI accelerator PCB design with our comprehensive guide. Explore 30+ layer stackups, ultra-low loss materials, and signal integrity rules for H100 and H200 GPU boards.

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AI Training vs AI Inference: Why They Need Different PCB Designs

Posted on June 05, 2026 by Arya Li

AI training and inference impose fundamentally different demands on PCB design. This guide breaks down compute density, memory bandwidth, interconnect, power delivery, and thermal requirements for each workload—and what they mean for board design and manufacturing.

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H100 vs MI300X: NVIDIA vs AMD AI Accelerator Comparison

Posted on June 04, 2026 by Arya Li

A hardware engineer's comparison of NVIDIA H100 and AMD MI300X—compute performance, memory architecture, interconnect, power delivery, PCB design requirements, and which platform suits your AI workload.

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What Is an OAM Module? Open Accelerator Module Standard for AI Hardware

Posted on June 04, 2026 by Stacy Lu

OAM (Open Accelerator Module) explained for hardware engineers: OCP standard architecture, module types, electrical interface, PCB design requirements, and how OAM shapes AI accelerator manufacturing.

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What Is NVSwitch? The Silicon Behind NVIDIA's GPU Cluster Scale-Out

Posted on June 05, 2026 by Stacy Lu

NVSwitch explained for hardware engineers: how NVIDIA's switch chip enables fully connected GPU clusters, its evolution across generations, PCB routing requirements, and what it means for AI server board design.

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GPU Server Architecture Explained: Boards, Slots, Power Planes and Cooling Zones

Posted on June 12, 2026 by Julia Wu

Discover the ultimate guide to AI GPU server architecture. Learn about GPU server design, baseboards, OAM/SXM slots, power planes, cooling zones, and advanced PCB manufacturing.

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OCP OAM vs. NVIDIA SXM: AI GPU Form Factors and Baseboard PCB Design

Posted on June 12, 2026 by Julia Wu

Discover the key differences between OCP OAM and NVIDIA SXM AI GPU form factors. Learn how these architectures impact universal baseboard (UBB) PCB design, high-speed routing, and thermal management in AI servers.

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A100 vs H100: GPU Generational Leap & PCB Stack Differences Explained

Posted on June 12, 2026 by Arya Li

A hardware engineer's deep dive into A100 vs H100—architecture differences, PCB layer count, materials, signal integrity, power delivery, and what changes on the manufacturing floor.

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NVIDIA Blackwell Architecture Explained: B200, GB200 & PCB Design Impact

Posted on June 12, 2026 by Arya Li

A hardware engineer's guide to NVIDIA Blackwell architecture—B200 and GB200 GPU specs, CoWoS packaging, NVLink 5.0, and what all of it means for PCB stackup, materials, and manufacturing.

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What Is an AI Server? Architecture, Components & PCB Requirements

Posted on June 12, 2026 by Stacy Lu

Understand AI server architecture from a hardware engineer's perspective—key components, PCB design challenges, manufacturing requirements, and how NextPCB supports AI server production.

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H100 vs H200 vs B200: Best NVIDIA GPU for AI Infrastructure 2026

Posted on June 12, 2026 by Stacy Lu

Compare NVIDIA H100, H200, and B200 for AI infrastructure—specs, PCB design requirements, thermal demands, and how to choose the right GPU for your workload.

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EMI and EMC Reduction Techniques in PCB Design

Posted on June 04, 2026 by NextPCB Content Team - iotbyhvm

Learn effective EMI and EMC reduction techniques in PCB design, including grounding, stackup, routing, decoupling, and shielding methods for high-speed circuits.

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Tag: EMI PCB design pcb grounding EMC Design signal integrity (SI) PCB Shielding high-speed design

Two Ways to Create Blind and Buried Vias in Cadence Allegro

How to Add and Plan Multi-layer PCB Stackups in Altium Designer?

Choosing the Right Substrate Materials for PCB Manufacturing: A Comprehensive Guide

Bulk Capacitor vs Decoupling Capacitor: Understanding the Three-Tier Capacitor Strategy

ESR and ESL in Capacitors: What They Mean and Why They Matter in PCB Power Integrity

X7R vs C0G vs X5R: MLCC Dielectric Types Explained for PCB Engineers

Decoupling Capacitor Placement: Rules & Strategies for High-Speed PCB

Accelerator PCB PDN Design: VRM & Decoupling Guide

AI Accelerator PCB Design Guide: Layers, Materials and Signal Integrity for H100/H200 Boards

AI Training vs AI Inference: Why They Need Different PCB Designs

H100 vs MI300X: NVIDIA vs AMD AI Accelerator Comparison

What Is an OAM Module? Open Accelerator Module Standard for AI Hardware

What Is NVSwitch? The Silicon Behind NVIDIA's GPU Cluster Scale-Out

GPU Server Architecture Explained: Boards, Slots, Power Planes and Cooling Zones

OCP OAM vs. NVIDIA SXM: AI GPU Form Factors and Baseboard PCB Design

A100 vs H100: GPU Generational Leap & PCB Stack Differences Explained

NVIDIA Blackwell Architecture Explained: B200, GB200 & PCB Design Impact

What Is an AI Server? Architecture, Components & PCB Requirements

H100 vs H200 vs B200: Best NVIDIA GPU for AI Infrastructure 2026

EMI and EMC Reduction Techniques in PCB Design

Categories

Recommended Article:

BLOG

Two Ways to Create Blind and Buried Vias in Cadence Allegro

How to Add and Plan Multi-layer PCB Stackups in Altium Designer?

Choosing the Right Substrate Materials for PCB Manufacturing: A Comprehensive Guide

Bulk Capacitor vs Decoupling Capacitor: Understanding the Three-Tier Capacitor Strategy

ESR and ESL in Capacitors: What They Mean and Why They Matter in PCB Power Integrity

X7R vs C0G vs X5R: MLCC Dielectric Types Explained for PCB Engineers

Decoupling Capacitor Placement: Rules & Strategies for High-Speed PCB

Accelerator PCB PDN Design: VRM & Decoupling Guide

AI Accelerator PCB Design Guide: Layers, Materials and Signal Integrity for H100/H200 Boards

AI Training vs AI Inference: Why They Need Different PCB Designs

H100 vs MI300X: NVIDIA vs AMD AI Accelerator Comparison

What Is an OAM Module? Open Accelerator Module Standard for AI Hardware

What Is NVSwitch? The Silicon Behind NVIDIA's GPU Cluster Scale-Out

GPU Server Architecture Explained: Boards, Slots, Power Planes and Cooling Zones

OCP OAM vs. NVIDIA SXM: AI GPU Form Factors and Baseboard PCB Design

A100 vs H100: GPU Generational Leap & PCB Stack Differences Explained

NVIDIA Blackwell Architecture Explained: B200, GB200 & PCB Design Impact

What Is an AI Server? Architecture, Components & PCB Requirements

H100 vs H200 vs B200: Best NVIDIA GPU for AI Infrastructure 2026

EMI and EMC Reduction Techniques in PCB Design

Categories

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