Stripline Impedance Calculator

Quickly estimate the characteristic impedance of a symmetric internal-layer PCB trace using the IPC-2141 stripline formula. A fast single-geometry check — for full stackup design, see our complete impedance calculator.

Stripline Parameters

Trace Width (W) *

Plane-to-Plane Spacing (H) *

Copper Thickness (T) *

1oz ≈ 1.378 mil (35μm) finished copper.

Dielectric Constant (E_r) *

Uses the IPC-2141 simplified symmetric stripline formula. See our Microstrip Calculator for external-layer traces, or the full stackup impedance tool for a manufacturable stackup match.

Estimated Stripline Impedance

Characteristic Impedance

0.00 Ω

Z₀, symmetric stripline

Effective Dielectric Constant (ε_eff) 0.00

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Calculation Reference

This calculator uses the IPC-2141 simplified closed-form formula for symmetric stripline: an internal-layer trace centered exactly midway between two reference planes, fully embedded in dielectric on both sides.

Note: this formula assumes a symmetric (centered) stripline. An off-center trace needs a separate asymmetric correction — see the FAQ.

Z₀ = 60/√E_r × ln( 4H / (0.67π(0.8W+T)) )

ε_eff = E_r (fully homogeneous dielectric, no air exposure)

Source: IPC-2141, "Controlled Impedance Circuit Boards and High Speed Logic Design."

Frequently Asked Questions

What is symmetric stripline, and how is it different from microstrip?

Symmetric stripline is an internal-layer trace sandwiched exactly midway between two ground or power planes, fully embedded in dielectric on both sides. Because it has no exposure to air, stripline's effective dielectric constant simply equals the laminate's bulk E_r, unlike microstrip, which is only partially surrounded by dielectric and has a lower effective E_r.

How is stripline impedance calculated?

This calculator uses the IPC-2141 simplified symmetric stripline formula, Z₀ = (60 / √E_r) × ln(4H / (0.67π(0.8W + T))), where H is the total distance between the two reference planes (with the trace centered between them), W is trace width, T is copper thickness, and E_r is the dielectric constant. This assumes the trace sits exactly in the middle; an off-center (asymmetric) stripline needs a different formula, noted below.

What if my trace isn't exactly centered between the two planes?

This calculator assumes a symmetric stripline, with the trace equidistant from both reference planes. If your stackup places the trace off-center, closer to one plane than the other, that's an asymmetric (offset) stripline, which requires a separate correction formula and will have a somewhat different impedance than this symmetric result for the same total plane-to-plane spacing. Treat this calculator's result as an approximation in that case, and verify the offset stripline value with your fabricator's field solver.

Why do designers choose stripline over microstrip for sensitive signals?

Being fully enclosed between two reference planes gives stripline better natural shielding against external EMI and reduces radiated emissions compared to microstrip, since the fields are largely contained within the dielectric rather than partly exposed above the board. This makes stripline a common choice for sensitive analog signals, RF routing that needs isolation from other traces, and designs with strict EMC requirements, at the cost of needing an internal layer and generally requiring wider traces than microstrip for the same impedance target.

Should I use this or the full NextPCB stackup impedance tool?

Use this calculator for a quick single-geometry estimate when you already know roughly what internal-layer spacing you're working with. If you're still deciding on layer count, board thickness, or copper weights, or you want trace width and spacing solved directly against one of NextPCB's real, manufacturable stackups, use the full PCB Controlled Impedance Calculator instead, which also returns a recommended stackup rather than just a geometry.

How accurate is this compared to a 2D field solver?

IPC-2141's closed-form equations are widely used for early-stage sizing and are generally within a few percent of a full field solver for typical PCB geometries, but they don't model the trapezoidal etch profile of real copper or glass-weave effects in the laminate, and they assume the symmetric case described above. For tightly toleranced designs, verify the final geometry with your fabricator's field solver or a TDR-tested impedance coupon before committing to production.