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PCB Via Current Calculator

Estimate the current-carrying capacity, resistance, voltage drop, and power loss of a plated via based on the IPC-2221 conductor model. Enter your hole diameter and copper plating thickness to compare through-hole and buried/blind vias before you route your power paths.

Via Parameters

The drilled/finished hole diameter, not the pad diameter.

Through-hole: use full board thickness. Buried/blind: use only the span between the connected layers.

Calculations reuse the IPC-2221 generic conductor model applied to the via's equivalent copper cross-section. See our Trace Width Calculator for the same standard applied to traces.

Estimated Current-Carrying Capacity

 

Through-Hole Via

D t
0.00 A

Pads exposed at outer surface (like an external trace)

0.00 mΩ
Resistance
0.00 V
Volt. Drop
0.00 W
Power Loss
 

Buried / Blind Via

D t
0.00 A

Fully embedded in dielectric (like an internal trace)

0.00 mΩ
Resistance
0.00 V
Volt. Drop
0.00 W
Power Loss

Estimated value only. Validate with thermal simulation for high-current designs.

Ready for Fabrication?

NextPCB supports mechanical drill sizes from 0.15mm to 6.5mm, with blind/buried via copper plating down to about 20μm.

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Calculation Reference

IPC-2221 does not publish a dedicated via current-capacity table. This calculator applies IPC-2221's generic conductor model to the via barrel by treating the thin plated cylinder as an equivalent flat conductor: its cross-sectional area is calculated from the hole diameter and wall copper thickness, then used in the same current-vs-area relationship applied on our Trace Width Calculator. Treat results as a design estimate, not a certified rating.

  • k = 0.048 for Through-Hole Vias (surface-exposed)
  • k = 0.024 for Buried / Blind Vias (fully embedded)
Equivalent Area (mils²) = π × WallThickness × ( HoleDiameter + WallThickness )
Current (A) = k × TempRise0.44 × Area0.725

Once the current is known, resistance, voltage drop, and power loss are calculated from the via's physical dimensions and copper's resistivity, corrected for the via's estimated operating temperature (Ambient + Temp Rise).

  • ρ (copper @ 25°C) = 1.7 × 10⁻⁶ Ω·cm
  • α (temp. coefficient) = 0.0039 / °C
Resistance (Ω) = ρ × Length / Area × ( 1 + α × ( Tvia - 25 ) )
Voltage Drop (V) = Current × Resistance
Power Loss (W) = Current² × Resistance

Frequently Asked Questions

How is a via's current-carrying capacity calculated from hole diameter and plating thickness?

This calculator treats the plated via barrel as an unrolled conductor: the copper lining the hole wall forms a thin cylindrical shell, and its cross-sectional area is calculated as pi times the wall copper thickness times the sum of the hole diameter and the wall thickness. That equivalent area is then used in the same IPC-2221 current-versus-area relationship used for trace width, solving for current instead of width.

Does IPC-2221 officially define a formula for via current capacity?

No. IPC-2221 defines its current-carrying formula for flat, straight copper traces, not for cylindrical via barrels. Treating the via wall as an equivalent flat conductor is a widely used engineering approximation, not an officially published IPC-2221 via table, so results should be treated as a design estimate rather than a certified rating.

Why does a buried or blind via carry less current than a through-hole via of the same size?

A through-hole via has copper pads exposed at the outer surface, where heat can convect away into open air, similar to an external trace. A buried or blind via is fully sandwiched inside the dielectric stack, which conducts heat away far less efficiently, similar to an internal trace. This calculator applies the lower internal-layer constant (k = 0.024) to buried and blind vias and the higher external-layer constant (k = 0.048) to through-hole vias to reflect that difference.

How much copper plating thickness should I use for a via?

Most fabricators, including NextPCB, plate blind and buried via walls to a minimum of about 20 micrometers (roughly 0.8 mil) of copper, which is a common IPC Class 2 baseline. Higher-reliability designs or high-current vias often specify thicker plating; check your fabricator's current capability documentation before finalizing this value, since it directly limits achievable current density.

What via barrel length should I enter for the resistance calculation?

Enter the length of copper the current actually travels through: for a through-hole via, that is typically the finished board thickness; for a blind or buried via, it is only the distance between the layers it connects, which is usually much shorter. Using the wrong length will skew the resistance, voltage drop, and power loss results even though the current-capacity number is unaffected.

Should I rely on a single via for high-current paths, or use multiple vias?

For power and ground connections carrying more than a fraction of an amp, most designers use multiple vias in parallel rather than a single large via, since paralleling vias lowers total resistance, distributes thermal load, and adds redundancy if one via is compromised during fabrication or in service. This calculator estimates the capacity of a single via; multiply by the number of parallel vias for a rough combined estimate, keeping in mind that current does not always split perfectly evenly.