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PCB Via Parasitic Inductance Calculator | NextPCB
 

PCB Via Parasitic Inductance Calculator

Estimate a via's parasitic inductance from its length and diameter, and see the resulting inductive reactance at your signal's rise time. Useful for checking decoupling vias and power/ground via stitching on high-speed designs.

Via Parameters

The finished (drilled) hole diameter. Has a much smaller effect on inductance than via length.

See our Via Capacitance Calculator and Via Current Calculator for related via sizing tools.

Estimated Via Inductance

 

Via Inductance

h d
0.00 nH

Series parasitic inductance of the via barrel

 

Inductive Reactance

Xₗ
0.00 Ω

Impedance this via presents at your signal's rise time

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NextPCB supports back-drilling and blind/buried vias to help shorten via length and reduce parasitic inductance on high-speed designs.

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Calculation Reference

This calculator uses the standard closed-form approximation for the self-inductance of a via, treating it as a short cylindrical conductor. Dimensions are converted to inches internally, and the result is reported in nanohenries. Notice diameter (d) sits inside a logarithm while length (h) is a direct multiplier — length dominates the result far more than diameter does.

  • h = via length (current path through the board)
  • d = via diameter (finished hole)
Inductance (nH) = 5.08 × h × [ ln( 4h / d ) + 1 ]
( h, d in inches )

Once inductance is known, the inductive reactance it presents to a signal depends on how fast that signal's edges are — faster rise times push more energy to higher frequencies, which a fixed inductance opposes more strongly.

Reactance (Ω) = π × L / T10-90%

Frequently Asked Questions

What is via parasitic inductance and why does it matter?

Every via has a small series inductance from the current loop formed as it passes through the board. On high-speed digital designs, this is often more disruptive than via parasitic capacitance: it weakens the effectiveness of nearby decoupling capacitors, adds impedance that reflects fast signal edges, and can create resonances with the via's own parasitic capacitance at high frequencies.

How is the L = 5.08h[ln(4h/d) + 1] formula derived?

This is a widely used closed-form approximation (from Johnson and Graham's high-speed digital design work) for the self-inductance of a short cylindrical conductor. Here h is the via's length (the distance current travels through the board) and d is the via's finished hole diameter; both are entered in inches internally, and the result is reported in nanohenries.

Why does via diameter have so little effect on inductance compared to via length?

Diameter only appears inside a logarithm in the formula, while length appears as a direct linear multiplier, so doubling the via length roughly doubles the inductance, while doubling the diameter barely moves the result. This is why reducing board thickness, or using a shorter via such as a blind or buried via, is a far more effective way to cut via inductance than simply drilling a larger hole.

How can I reduce via inductance in a real design?

The most effective options are shortening the current path (using blind, buried, or back-drilled vias instead of a full through-hole via on a thick board), and placing multiple vias in parallel, since parallel inductances combine to a lower total value, similar to parallel resistors. Placing ground vias close to a signal or power via also lowers the effective loop inductance by tightening the current return path.

What is inductive reactance and how does signal rise time affect it?

Inductive reactance is the impedance a via's inductance presents to a changing signal, and it scales inversely with rise time: a faster edge (shorter 10-90% rise time) pushes more of the signal's energy into higher frequencies, which the same inductance opposes more strongly. This calculator estimates that reactance as pi times the inductance divided by the signal's rise time, so the same physical via becomes a bigger problem as your signal edges get faster.

How does via inductance affect decoupling capacitor performance?

A decoupling capacitor only works as well as the connection between it and the IC it protects, and that connection almost always includes at least one via. The via's parasitic inductance adds directly to the capacitor's own effective series inductance, raising the frequency at which the capacitor stops being effective, so minimizing via inductance on decoupling paths is one of the most direct ways to improve power delivery at high frequencies.

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