PCB Via Parasitic Capacitance Calculator

Estimate a via's parasitic capacitance from pad diameter, antipad (clearance) diameter, board thickness, and dielectric constant. Use it to flag vias that may need a larger antipad before they slow your high-speed signal edges.

Via Parameters

Via Length (h) *

Via Diameter (d) *

The finished (drilled) hole diameter. Has a much smaller effect on inductance than via length.

Signal Rise Time (10–90%)

See our Via Capacitance Calculator and Via Current Calculator for related via sizing tools.

Estimated Parasitic Capacitance

0.00 pF

Parasitic capacitance at the pad-to-plane interface

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Calculation Reference

This calculator uses the standard closed-form approximation for via parasitic capacitance at a single pad-to-plane interface, treating the pad and the surrounding plane as a parallel-plate capacitor. Dimensions are converted to inches internally, and the result is reported in picofarads.

d1 = pad diameter
d2 = antipad (clearance) diameter, must be > d1
h = dielectric thickness between pad and reference plane
Er = dielectric constant of the material between them

Capacitance (pF) = 1.41 × Er × h × d1 / ( d2 − d1 )

( h, d1, d2 in inches )

Frequently Asked Questions

What is via parasitic capacitance and why does it matter?

When a via passes through a ground or power plane, the copper pad, the plane's copper, and the dielectric between them form a small parallel-plate-like capacitor. This parasitic capacitance is normally negligible, but on high-speed signal paths it can slow signal edges, create impedance discontinuities, and contribute to reflections, so designers estimate it to judge whether a via needs a larger antipad or a different stackup.

How is the via capacitance formula derived?

This is a widely used closed-form approximation (popularized in Howard Johnson and Martin Graham's high-speed digital design work) that models the via pad and the surrounding plane as a simple parallel-plate capacitor with fringing effects folded into the constant 1.41. Here d1 is the pad diameter, d2 is the antipad (clearance) diameter in the plane layer, h is the dielectric thickness between the pad and the plane, and Er is the dielectric constant of the material between them; the result is in picofarads when the dimensions are entered in inches.

How does increasing the antipad (clearance) diameter reduce via capacitance?

Capacitance is inversely related to the gap between the pad and the surrounding plane, represented by (d2 - d1) in the denominator. A larger antipad increases that gap, which reduces capacitance, but an oversized antipad also removes more copper from the plane, which can weaken the return-current path and increase plane impedance, so antipad size is usually a trade-off rather than a value to maximize.

What via parasitic capacitance is considered acceptable for high-speed signals?

There's no single universal threshold, but many signal integrity engineers treat via capacitance in the low tenths of a picofarad as usually insignificant, while values approaching or exceeding roughly half a picofarad are often flagged for review on multi-gigabit or fast-edge designs, where the resulting rise-time degradation and impedance dip become large relative to the signal's rise time. Always weigh this calculator's estimate against your actual signal rise time and target impedance rather than a fixed cutoff.

Which dielectric constant (Er) value should I use?

Use the dielectric constant of the material directly between the via pad and the reference plane, not a generic FR4 average. Standard FR4 is often quoted around 4.2 to 4.5 at low frequency, but Er drops somewhat as signal frequency increases and varies with resin content and prepreg type, so check your fabricator's or laminate supplier's frequency-dependent Dk table for high-speed designs.

Does this formula account for multi-layer stackups, or just a single plane?

This formula models the capacitance contributed by one pad-to-plane interface, using the dielectric thickness (h) between that pad and the nearest reference plane. If a via passes multiple planes, each pad-to-plane gap contributes its own parasitic capacitance, and the total loading on the via is the sum of those individual contributions rather than a single calculation using the full board thickness.