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Introduction
112G PAM4 became the standard interconnect speed for data center switching and AI server NICs over the course of 2021–2024. Before that standard is fully mature in deployment, the industry is already transitioning to 224G. The bandwidth demands of AI training clusters—where thousands of GPUs must exchange gradient data at rates that dwarf any previous distributed computing application—are the primary force driving this transition. A single NVIDIA B200 GPU produces up to 1,800 GB/s of NVLink traffic. Connecting hundreds of such GPUs in a training cluster requires switch and NIC fabrics operating at the highest per-lane bandwidth physically achievable on a printed circuit board.
224G (224 Gb/s per lane, PAM4) is that next speed tier. It doubles the per-lane throughput of 112G while operating at double the symbol rate (112 GBaud vs 56 GBaud). The doubled symbol rate raises the Nyquist frequency from 28 GHz to 56 GHz—a frequency at which PCB channel loss is severe enough that every material, geometry, and manufacturing choice must be optimized simultaneously to achieve a compliant channel. There is no comfortable margin at 224G. Every decibel counts.
This article explains the engineering fundamentals of 224G PCB design, from channel loss budget through laminate selection, via design, copper foil, routing rules, and simulation requirements. It is written for PCB layout engineers and hardware designers who need to understand what changes—and what becomes impossible—when moving from 112G to 224G on a printed circuit board.
AI training clusters are the primary driver of 224G adoption. The scale of bandwidth required in a modern GPU cluster is difficult to appreciate without specific numbers. A single rack of NVIDIA GB200 NVL72 systems contains 72 B200 GPUs each with 1,800 GB/s of NVLink 5.0 bandwidth, plus eight 400G InfiniBand links per rack for inter-rack communication. Scaling to a cluster of 10,000 GPUs—a typical size for frontier LLM training runs in 2026—requires a network fabric capable of sustaining hundreds of terabits per second of aggregate bandwidth between racks.
At 112G PAM4, an 800G port (8 × 112G) is the current state of the art for switch-to-server connections. The next tier—1.6T ports built from 8 × 224G lanes—doubles the per-port bandwidth without increasing the port count or cable count. This is critically important for AI infrastructure because the rack density constraints of data centers make adding more physical ports increasingly difficult. 224G allows the industry to double interconnect capacity within the same physical infrastructure envelope.
Beyond AI clusters, 224G is being driven by co-packaged optics (CPO), where optical transceivers are integrated directly onto the switch ASIC package substrate. CPO eliminates the PCB channel between the switch ASIC and the optical module, but the electrical lanes from the ASIC die to the optical engine within the CPO package must still operate at 224G. Understanding 224G PCB design is therefore relevant even for CPO implementations, because the board-level channel from the CPU/NPU host to the CPO switch ASIC must be designed for 224G signaling.
224G uses PAM4 (Pulse Amplitude Modulation, 4 levels) signaling at 112 GBaud. With 2 bits per symbol (log2(4) = 2), the effective data rate is 112 GBaud × 2 bits/symbol = 224 Gb/s per lane. The Nyquist frequency—the frequency at which the channel must exhibit adequate insertion loss for a compliant eye diagram—is half the symbol rate: 112 GBaud / 2 = 56 GHz.
Key 224G signal characteristics for PCB design:
| Parameter | 112G PAM4 | 224G PAM4 |
|---|---|---|
| Symbol rate (GBaud) | 56 | 112 |
| Modulation | PAM4 | PAM4 |
| Bits per symbol | 2 | 2 |
| Nyquist frequency | 28 GHz | 56 GHz |
| UI (Unit Interval) | 17.86 ps | 8.93 ps |
| Voltage margin per eye | ⅓ of differential swing | ⅓ of differential swing (same fraction, smaller absolute voltage due to lower transmitter swing at higher frequency) |
| Typical host-to-switch channel length | 30–80 mm on-board | 10–40 mm on-board (severely constrained) |
| FEC requirement | Mandatory (KP4 or RS-FEC) | Mandatory (stronger FEC; pre-FEC BER limit < 10−3) |
The doubled Nyquist frequency from 28 GHz (112G) to 56 GHz (224G) is the single most consequential specification change from a PCB design perspective. Dielectric loss scales approximately linearly with frequency; conductor (skin-effect) loss scales approximately as the square root of frequency. Moving from 28 GHz to 56 GHz approximately doubles dielectric loss and increases conductor loss by approximately 40% for the same material and trace geometry. The combined effect is that a channel that barely met the 112G insertion loss budget will exceed the 224G budget by a large margin—requiring either a much shorter channel, a much better material, or both.
Understanding 224G PCB design starts with a clear picture of which channel impairments approximately double with the Nyquist frequency and which do not.
What approximately doubles (scales with frequency):
What increases but less than proportionally:
What does not change with frequency:
The practical consequence is that 224G channels are approximately 40–50% shorter than 112G channels on the same material, all other things being equal. A 112G channel designed for 60 mm on Megtron 7 with HVLP copper might achieve < 10 dB insertion loss at 28 GHz; the same 60 mm channel at 56 GHz might show 18–20 dB insertion loss—potentially outside the 224G budget depending on via and connector contributions. The 224G channel on the same material must be shortened to approximately 30–35 mm to achieve equivalent insertion loss at 56 GHz.
For the 112G context and how it shaped the current PCB design discipline, see the 112G PAM4 PCB Design guide.
The 224G channel loss budget depends on the specific standard being implemented. IEEE 802.3df (400G and 800G Ethernet using 224G lanes), OIF-CEI-224G, and emerging switch ASIC vendor specifications each define their own channel compliance envelopes, but all share the common feature of a severely constrained insertion loss budget at 56 GHz.
A representative channel loss budget for a 224G on-board channel (ASIC package to retimer or optical engine, no external connector):
| Loss Contributor | 112G Typical (at 28 GHz) | 224G Target (at 56 GHz) | Notes |
|---|---|---|---|
| PCB trace (dielectric) | 5–10 dB | 5–10 dB | Shorter channel required to keep within budget at 56 GHz |
| PCB trace (conductor) | 2–4 dB | 3–6 dB | ~41% higher at 56 GHz vs 28 GHz on same foil |
| Via structures (launch + transition) | 0.5–2 dB | 1–3 dB | Stub resonances within band if not eliminated; anti-pad capacitance higher impact |
| Package launch (ASIC/retimer) | 0.5–1.5 dB | 0.5–2 dB | Package substrate routing loss increases with frequency |
| Connector (if present) | 0.5–2 dB | 1–3 dB (if used) | Connectors rated to 56 GHz are extremely limited; avoid in 224G channels |
| Total budget (typical compliant channel) | < 15–20 dB at 28 GHz | < 10–15 dB at 56 GHz (practical design target) | 224G boards must be designed to significantly better than the raw spec limit to maintain PAM4 eye margin |
The practical 224G channel design target of < 10–15 dB at 56 GHz is dramatically tighter than the 112G equivalent (< 20 dB at 28 GHz was typically achievable on well-designed channels). This budget forces 224G channels to be short, use the best available materials, eliminate all via stubs, and minimize every other source of loss simultaneously. There is no room to compensate for a suboptimal material choice with a shorter channel, or a longer channel with better material: the budget is tight enough that all parameters must be optimized together.
Standard Megtron 6 (Df ~0.004 at 10 GHz) is demonstrably inadequate for 224G PCB channels of any practical length. Even Megtron 6E and Tachyon 100G (Df ~0.002–0.003 at 10 GHz)—excellent materials for NVLink 4.0 and PCIe Gen5 as discussed in the high-speed PCB materials guide—are marginal for 224G channels beyond approximately 20 mm. At 56 GHz, even the best commercially available hydrocarbon laminates have Df values that generate significant channel loss per centimeter.
The laminate hierarchy for 224G signal layers:
| Laminate | Df (10 GHz) | Df (50 GHz, approx.) | 224G Suitability | Max Practical Channel (224G) |
|---|---|---|---|---|
| Panasonic Megtron 6 | ~0.004 | ~0.007–0.009 | Not suitable | < 10 mm (unusable) |
| Panasonic Megtron 6E | ~0.0024 | ~0.004–0.005 | Marginal for very short channels | < 15–20 mm with optimized vias |
| Panasonic Megtron 7 | ~0.002 | ~0.003–0.004 | Minimum viable; good for short channels | 20–30 mm with HVLP copper and laser vias |
| Isola Astra MT77 | ~0.002 | ~0.003–0.004 | Minimum viable (similar to Megtron 7) | 20–30 mm with HVLP copper and laser vias |
| Rogers RO3003 (PTFE) | ~0.001 | ~0.001–0.002 | Good; best performance among commercial options | 35–50 mm with HVLP copper and laser vias |
| Rogers RO3003G2 | ~0.001 | ~0.0012 | Best available for production PCBs | 40–55 mm under ideal conditions |
| Taconic TLY-5 (PTFE) | ~0.0009 | ~0.001 | Best-in-class; processing challenges | 50+ mm with optimized design |
PTFE-based laminates (Rogers RO3003, Taconic TLY series) provide the lowest Df at 56 GHz among commercially available materials, making them the preferred choice for 224G signal layers wherever the design requires channels longer than approximately 25 mm. However, PTFE processing in multilayer boards has well-documented challenges: PTFE does not bond reliably to standard inner layers without surface preparation (plasma etch or sodium naphthalide treatment); PTFE's very low CTE mismatch with copper creates bonding stress during thermal cycling; and PTFE's softness makes via drilling and laser processing less predictable than with glass-reinforced laminates.
Many 224G board designs use a hybrid stackup: PTFE-based laminates on the 224G signal layers and Megtron 7 on NVLink 5.0 and other ultra-high-speed layers, with Megtron 6 on power, ground, and management layers. The laminate compatibility and bonding chemistry for each interface in this hybrid stack must be explicitly qualified before production. This is an extension of the hybrid stackup approach described in the high-speed materials guide, taken to a more extreme level by the addition of PTFE layers.
At 56 GHz, skin depth in copper is approximately 0.28 μm—less than one-third of what it is at 28 GHz (approximately 0.43 μm). This extreme skin confinement means that the current flows in an even thinner surface layer than at 112G frequencies, and the roughness of that surface has a proportionally larger impact on conductor loss. The relationship between foil roughness and conductor loss at 56 GHz follows the Hammerstad-Jensen model; for a rougher foil with Rz = 2 μm (VLP grade), the roughness correction factor at 56 GHz raises the effective conductor resistance by approximately 2.5× over the smooth-foil value. For HVLP foil with Rz = 0.5 μm, the correction factor is approximately 1.5×.
The practical consequence is that the conductor loss difference between VLP and HVLP copper is proportionally larger at 56 GHz than at 28 GHz. On a 25 mm trace, switching from VLP (Rz ~1.5 μm) to HVLP (Rz ~0.5 μm) saves approximately 0.8–1.2 dB of conductor loss at 56 GHz—a meaningful fraction of the tight 224G channel budget. HVLP copper is therefore not just best practice for 224G; it is effectively required on any 224G signal layer where the channel length exceeds approximately 15 mm.
Some advanced 224G designs specify electroless copper (ECD) plating on the via walls with a controlled low-roughness finish, as via wall roughness also contributes to skin-effect loss at 56 GHz. This requires specialized via plating chemistry beyond standard PCB production and is currently at the frontier of what commercial fabricators can achieve.
Via stubs create insertion loss notches at their resonance frequencies. For a through-hole via stub of length L in a material with propagation velocity vp, the first resonance occurs at fnull = vp / (4L). At 56 GHz, a stub of only 0.75 mm length creates a resonance at exactly 56 GHz—directly at the 224G Nyquist frequency. A 0.5 mm stub creates a resonance at approximately 85 GHz, whose skirt still adds measurable loss at 56 GHz. Even a 0.3 mm (approximately 12 mil) stub creates a resonance at approximately 140 GHz, which is marginally acceptable.
The implication is clear: through-hole via stubs on 224G signal paths must be either completely eliminated (by using blind/buried laser microvias instead of through-holes) or reduced to < 0.2 mm (approximately 8 mils) by precision backdrilling. Achieving < 0.2 mm residual stubs with backdrilling requires:
For most 224G PCB designs, blind laser microvias are preferred over backdrilled through-holes because they eliminate stubs entirely and provide cleaner via launch geometry. Sequential build-up HDI with stacked microvias—the same technology already in use for NVLink 5.0 routing on B200 boards as described in the HDI PCB guide—is the standard via approach for 224G signal layers.
Anti-pad geometry also requires more careful optimization for 224G than for 112G. The shunt capacitance of a through-hole via anti-pad at 56 GHz creates a local impedance dip that is proportionally larger than at 28 GHz for the same geometry. Larger anti-pads reduce the capacitance discontinuity, but remove too much reference plane copper. The optimal anti-pad diameter for 224G via transitions is typically 20–30% larger than the equivalent 112G design, compensating for the higher-frequency impedance sensitivity while maintaining adequate reference plane coverage.
224G trace routing rules are stricter than 112G in every dimension. The following rules represent best practice for 224G differential pair routing on a board using Megtron 7 or PTFE laminate with HVLP copper.
Differential impedance: 100 Ω ± 5% for standard differential pairs. At 56 GHz, impedance variations that would be acceptable at 28 GHz create proportionally larger reflections because the return loss budget is tighter. The manufacturing tolerance must be ± 5% on 224G signal layers; ± 10% as specified for PCIe Gen5 is inadequate.
Trace width: Narrower traces have higher resistance per unit length, which directly adds to conductor loss. However, narrower traces for the same impedance require a thinner dielectric (closer reference plane), which improves return loss and reduces via anti-pad capacitance. For 224G on Megtron 7 (Dk ~3.4) with 100 μm dielectric thickness, the 100 Ω differential impedance target corresponds to approximately 85–90 μm trace width with 80–90 μm intra-pair spacing. These very fine geometries (3.5–4 mil trace width) require laser direct imaging (LDI) for etching and electrolytic copper plating chemistry optimized for fine-line feature reproduction.
Intra-pair skew: < 0.5 ps per segment; < 1.5 ps full channel. The halved unit interval of 224G (8.93 ps vs 17.86 ps for 112G) means that the same absolute skew in picoseconds represents a larger fraction of the bit period, making mode conversion from intra-pair skew proportionally more damaging. Length matching to within 0.085 mm (corresponding to approximately 0.5 ps propagation delay in Megtron 7) is required.
Lane-to-lane spacing: 5W minimum (5 × trace width edge-to-edge) between adjacent differential pairs on the same layer. Crosstalk coupling power scales with frequency; at 56 GHz, the 4W rule adequate for PCIe Gen6 is not sufficient for 224G. The 5W rule keeps FEXT below −25 dB at 56 GHz for typical trace geometries. Where board area constraints force tighter spacing, shielding traces (ground traces between adjacent pairs) can mitigate crosstalk at the cost of routing complexity.
Maximum trace length (Megtron 7 + HVLP copper): Approximately 20–30 mm for a direct ASIC-to-retimer channel with no connectors and laser microvia transitions. Channels approaching 30 mm require full channel simulation to verify budget compliance. Channels beyond 30 mm on Megtron 7 are not reliably achievable without a retimer or an upgrade to PTFE-based laminate.
Reference plane continuity: No interruptions within 3 mm of any 224G trace. At 56 GHz, even small reference plane discontinuities (via anti-pad arrays, trace escapes through the reference layer, connector cutouts) create electromagnetic radiation and mode conversion at levels that are measurable and potentially budget-consuming. The reference plane on the layer immediately adjacent to each 224G signal layer must be a solid, uninterrupted ground pour.
224G equalization requirements are more demanding than 112G because the channel is shorter (less ISI to equalize from trace delay) but has more severe frequency-dependent loss and more challenging noise sources (higher crosstalk, more via-induced distortion at 56 GHz). The equalization architecture for 224G receivers typically includes:
A critical PCB design implication of 224G equalization: the equalizer can compensate for smooth, frequency-monotonic channel loss, but it cannot compensate for resonances (via stubs), mode conversion (from asymmetric traces or reference plane disruptions), or crosstalk (from adjacent lanes). These non-smooth impairments create pattern-dependent eye closure that reduces the effective PAM4 eye in ways that the equalizer cannot adapt to. The practical consequence is that 224G channel quality requirements are dominated not just by total insertion loss at 56 GHz but by the smoothness and predictability of the loss profile.
At 56 GHz, crosstalk coupling between adjacent differential pairs is high enough to be the primary channel design constraint in many 224G layouts—even more limiting than insertion loss. The reason is that crosstalk coupling voltage scales with frequency, while the PAM4 eye opening does not increase with frequency (it is fixed by the transmitter output swing, which if anything decreases at higher symbol rates). The result is that the crosstalk noise floor relative to the eye opening is proportionally higher at 56 GHz than at 28 GHz for the same physical layout.
FEXT (far-end crosstalk) is particularly damaging at 224G. FEXT arrives at the receiver at the same time as the desired signal (unlike NEXT, which arrives at the transmitter end and is spatially separated from the receiver). At 56 GHz, FEXT coupling coefficients for 3W spacing are approximately 2× what they are at 28 GHz for the same geometry. Moving to 5W spacing reduces FEXT coupling power by approximately 6–8 dB compared to 3W spacing, which is why the 5W rule is the recommended minimum for 224G rather than the 3W or 4W rules used for lower-speed interfaces.
In a dense 224G lane array (such as a 16-lane 3.2T interface on a switch ASIC), the worst-case FEXT is the sum of contributions from multiple aggressors on both sides of the victim lane. Simulation of the full lane array—not just a two-lane adjacent pair model—is required to assess worst-case FEXT in a dense 224G routing field. The simulation must include the effect of the ASIC package launches, which can produce stronger crosstalk coupling than the PCB traces alone due to the very close lane spacing within the package substrate.
Standard PCB connectors rated for 28 GHz (adequate for 112G) are not rated for 56 GHz. The number of commercially available connector families with verified S-parameter data to 56 GHz is extremely limited in 2025–2026. For 224G channel designs, the general approach is to avoid board-to-board connectors entirely on the 224G signal paths, routing 224G traces only on the same PCB from source ASIC to destination retimer or co-packaged optical engine.
When a board-to-board connection is unavoidable (for example, connecting a switch ASIC board to an optical line card via a midplane connector), the connector must be specifically rated for 112 GBaud operation, with measured S-parameters showing adequate insertion loss and return loss to 70 GHz. As of 2025, backplane connector families from Amphenol, TE Connectivity, and Molex capable of 112 GBaud operation are in development or early sampling stages; no mature, volume-production-available connector family exists for 224G backplane applications. This gap is a significant system architecture constraint and is one reason why co-packaged optics (CPO), which eliminates the board-to-board connector for the highest-speed signals entirely, is gaining rapid adoption at 224G.
Package launches at 224G—the transition from the ASIC package BGA ball through the PCB via to the signal trace—are the most loss-critical structures in the channel after the trace itself. The package substrate routing from the die to the BGA ball can contribute 0.5–2 dB of insertion loss at 56 GHz, depending on the package design. ASIC vendors typically provide differential S-parameter models of their package launch structures at 224G; these models must be included in the channel simulation to accurately budget all loss contributors.
Pre-layout simulation is not just recommended for 224G—it is required. The channel loss budget is tight enough that design decisions based on rules of thumb or extrapolation from 112G experience will regularly produce non-compliant channels. The 224G simulation workflow:
The simulation tools required for 224G include: a 3D EM solver capable of accurate results to 80 GHz (Ansys HFSS, CST Microwave Studio, Keysight EMPro); a 2D cross-section solver (Polar Si9000, Ansys Q3D); a SPICE or S-parameter channel simulator for full channel cascade; and IBIS-AMI model simulation for PAM4 eye diagram evaluation. The simulation workflow for 224G represents a significant investment of engineering time and requires expertise that not all PCB design teams have in-house.
In 2025–2026, 224G is beginning to appear in several locations within AI server and data center infrastructure, though it is not yet as broadly deployed as 112G.
Switch ASIC to retimer: The highest-bandwidth switch ASICs (targeting 51.2 Tb/s and above) use 224G lanes internally. The PCB channel from the switch ASIC package to the nearest retimer or co-packaged optical engine typically spans 10–30 mm and is the primary 224G PCB design challenge on switch line cards.
Co-packaged optics (CPO) electrical interface: In CPO designs, the optical transceivers are assembled on the same substrate as the switch ASIC, eliminating the PCB channel between the ASIC and the optics. However, the electrical interface from the NPU/CPU host to the CPO switch module still uses 224G electrical lanes over a short PCB distance. These channels are typically < 30 mm and represent the clearest near-term application of 224G PCB design.
Next-generation AI server NICs: 800G and 1.6T network interface cards for AI GPU clusters require 224G electrical lanes between the NIC ASIC and the optical transceiver cage. The NIC PCB channel must be designed to 224G specifications for these traces, even if most other signals on the NIC operate at lower speeds. The NVLink 5.0 and PCIe Gen6 interfaces on B200 boards discussed in the Blackwell architecture guide represent the current frontier of AI GPU interconnect; 224G Ethernet NICs are the parallel frontier for cluster-scale networking.
Future GPU-to-switch fabric: As NVLink scales beyond NVLink 5.0 and PCIe progresses beyond Gen6, it is expected that the next-generation GPU cluster fabric will require per-lane electrical speeds at or above 224G for the board-level traces connecting GPUs to switch silicon. This application—where 224G replaces NVLink 5.0 in a future GPU cluster fabric—represents the largest-scale potential deployment of 224G PCB design rules on AI server boards.
224G PCB manufacturing pushes fabrication capabilities to their limits in several dimensions simultaneously.
Fine-line etching: 80–90 μm trace width on 224G signal layers requires etching process control at ± 5 μm line width variation—tighter than the ± 8–10 μm achievable on standard production lines. This requires LDI (Laser Direct Imaging) for photoresist patterning (no film-based artwork), low-alpha aqueous alkaline etchant chemistry, and real-time etch rate monitoring across the production panel. Not all PCB fabricators have the combination of LDI, etch chemistry, and process control required for consistent 80–90 μm trace production in volume.
PTFE laminate processing: If PTFE laminates (Rogers RO3003, Taconic TLY series) are used on 224G signal layers, the fabricator must have qualified PTFE processing capability: plasma etch or sodium naphthalide surface treatment before lamination, specialized drill bit selection and parameters for PTFE drilling, and verified peel strength data for the PTFE-to-prepreg bond interface at the lamination cycle temperatures used for the rest of the stackup. PTFE compatibility with sequential lamination at temperatures above 180°C must be verified; some PTFE grades soften enough at standard press temperatures to affect dielectric thickness uniformity.
Laser microvia at 50–75 μm diameter: 224G BGA escape beneath fine-pitch ASIC packages may require microvias as small as 50 μm diameter—at the lower limit of production CO2 laser capability and firmly in UV laser territory. UV laser drill systems (Nd:YAG, excimer) can achieve 50 μm vias with adequate wall quality, but at lower throughput than CO2 systems. Stacked microvia alignment at 50 μm diameter requires optical registration accuracy of ± 10–15 μm—tighter than the ± 25 μm acceptable for 100 μm microvias on NVLink 5.0 boards.
Precision backdrilling (if used): For any 224G channels using through-hole vias with backdrilling, depth accuracy of ± 25 μm is required to achieve < 0.2 mm residual stubs. This is beyond the ± 50 μm standard for PCIe Gen5 backdrilling described in the PCIe Gen5 PCB design guide and requires per-panel depth file generation from profilometry measurements of the actual as-built stackup at multiple locations.
High-frequency electrical verification: TDR coupon measurements to verify impedance are standard for all high-speed boards. For 224G, VNA (Vector Network Analyzer) measurement of channel coupons to at least 80 GHz is required to verify that via structures, trace loss, and return loss all meet specification at 56 GHz. Few production PCB fabricators have in-house VNA capability to 80 GHz; third-party measurement services or customer-side verification at incoming inspection are the alternatives.
What is 224G PAM4 and how does it relate to 112G?
224G PAM4 is a serial electrical signaling standard operating at 112 GBaud (112 billion symbols per second) using four-level PAM4 encoding, achieving 224 Gb/s effective data rate per lane. It directly doubles the per-lane throughput of 112G PAM4 (56 GBaud, 112 Gb/s per lane) by doubling the symbol rate while keeping the same PAM4 modulation. The doubled symbol rate raises the Nyquist frequency from 28 GHz to 56 GHz, doubling the frequency content that the PCB channel must pass with adequate signal quality. For the 112G design foundation, the 112G PAM4 PCB Design guide provides the prerequisite context.
Can Megtron 7 be used for 224G PCB channels?
Megtron 7 (Df ~0.002 at 10 GHz) is viable for short 224G channels in the 15–25 mm range with HVLP copper and laser microvia transitions. For channels approaching 30 mm, the insertion loss budget becomes tight enough to require comprehensive channel simulation to verify margin. For channels beyond 30 mm, PTFE-based laminates (Rogers RO3003, Taconic TLY-5) with lower Df at 56 GHz are required. Most practical 224G switch ASIC to retimer channels on today's switch boards fall in the 15–25 mm range, making Megtron 7 a viable choice for those applications if HVLP copper is used throughout.
Why are connectors largely avoided in 224G PCB designs?
Standard PCB connectors are rated to frequencies of 20–40 GHz at most. At 56 GHz, connector contact discontinuities, housing resonances, and dielectric loss within the connector body create insertion loss and return loss contributions that consume a disproportionate fraction of the already-tight 224G channel budget. Connector-free on-board channels (from ASIC package to retimer on the same PCB) are the dominant 224G PCB topology for this reason. Co-packaged optics (CPO) takes this further by eliminating even the PCB channel between the ASIC and the optical engine, bringing the electrical signal path to its minimum possible length.
How short do 224G PCB traces actually need to be in practice?
On Megtron 7 with HVLP copper and laser microvia transitions, practical 224G on-board channels are 10–30 mm in length. Switch ASICs targeting 51.2 Tb/s with 224G lanes are designed with the retimer or CPO module placed within this distance on the PCB. Longer channels require PTFE laminates and/or retimers. The extremely short channel constraint is one reason why 224G board designs are dominated by very dense, compact layouts around the switch ASIC package—there is physically no room for extended routing at 56 GHz.
Is 224G relevant for GPU accelerator boards today?
Not directly for the GPU-to-baseboard interface, which uses NVLink 5.0 at 200 Gb/s per lane and PCIe Gen6 at 64 GT/s per lane in the current B200 generation. However, 224G is increasingly relevant for the network interface cards (NICs) used in GPU clusters, where 800G and 1.6T ports require 224G electrical lanes between the NIC ASIC and optical transceivers. As GPU cluster networks scale toward 3.2T and beyond, 224G PCB design rules will become standard knowledge for AI server hardware engineers even if NVLink itself is not at 224G per lane.
What simulation tools are required for 224G PCB design?
224G PCB simulation requires 3D electromagnetic solvers capable of accurate results to 80 GHz (HFSS, CST Microwave Studio, Keysight EMPro) for via and package launch characterization; 2D field solvers (Polar Si9000, Ansys Q3D) for trace cross-section impedance and loss-per-unit-length; SPICE or S-parameter channel cascade tools; and IBIS-AMI simulators for PAM4 eye diagram evaluation with transmitter and receiver equalization. The material Dk and Df characterization data must extend to at least 70 GHz, which requires laminate vendor measurements at high frequency rather than the standard 10 GHz datasheet values.
224G PCB design and manufacturing represents the current frontier of commercial PCB capability. NextPCB's advanced fabrication services cover ultra-low-loss laminate processing including PTFE-based materials, HVLP copper foil, fine-line etching to 80 μm trace widths, precision laser microvia drilling, controlled-depth backdrilling to ± 25 μm, and IPC Class 3 quality standards. Whether you are designing a 224G switch line card, a next-generation AI NIC, or planning for future GPU cluster fabric interconnects, NextPCB can support your program from prototype through production.
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