112G PAM4 PCB Design for AI Servers: Material Selection, Trace Routing and SI Rules

Introduction: As AI hardware demands unprecedented bandwidth to train massive LLMs and process inference workloads, the data center interconnects are rapidly shifting from 56G to 112G PAM4 (Pulse Amplitude Modulation 4-level). Designing a 112G PAM4 PCB introduces severe signal integrity (SI) challenges, including extreme insertion loss, crosstalk sensitivity, and tight impedance tolerances. This comprehensive guide explores essential 112G PCB design rules, optimal high-speed PCB materials, and trace routing techniques critical for next-generation AI server motherboards and accelerator cards.

1. Table of Contents
2. 1. The Shift to 112G PAM4 in AI Servers
3. 2. Understanding 112G PAM4: Nyquist Frequency and Math Fundamentals
4. 3. High-Speed Material Selection for 112G PCBs
5. 4. PCB Stackup, Copper Roughness, and Skew
6. 5. Trace Routing Rules for 112G Signal Integrity
7. 6. Via Optimization and Backdrilling
8. 7. Frequently Asked Questions (FAQ)
9. 8. Conclusion

1. The Shift to 112G PAM4 in AI Servers

The exponential growth of AI workloads requires massive data throughput between GPUs, CPUs, and network switches. To overcome the bandwidth bottlenecks, the industry has standardized on 112 Gbps per lane interfaces using PAM4 signaling. You will find these speeds natively supported in the latest switch silicon, OAM modules, and backplanes within modern AI server architectures.

For a hardware engineer, achieving a reliable high speed PCB AI design at 112G means treating the PCB not just as an electrical connection, but as a highly tuned microwave transmission line. Any microscopic deviation in manufacturing or layout can close the PAM4 signal eye diagram, resulting in unacceptable Bit Error Rates (BER).

For an overview of overall AI server architectures, refer to our AI Accelerator PCB Design Guide.

2. Understanding 112G PAM4: Nyquist Frequency and Math Fundamentals

Traditional NRZ (Non-Return-to-Zero) signaling uses two voltage levels (0 and 1) to transmit 1 bit per symbol. PAM4 uses four distinct voltage levels (-3, -1, +1, +3) to transmit 2 bits per symbol. This allows PAM4 to double the data rate without doubling the bandwidth.

For a 112 Gbps data rate using PAM4:

• Baud Rate: 112 Gbps / 2 bits/symbol = 56 GBaud
• Nyquist Frequency (f_Nyquist): 56 GBaud / 2 = 28 GHz

At 28 GHz, signal attenuation (Insertion Loss, denoted as S₂₁) and reflections (Return Loss, denoted as S₁₁) are severe. Furthermore, because PAM4 divides the voltage swing into three smaller eyes, the Signal-to-Noise Ratio (SNR) penalty is roughly 9.5 dB compared to NRZ. This means the 112G eye diagram is exactly 1/3 the height of a comparable NRZ eye, making it incredibly susceptible to crosstalk (NEXT/FEXT) and power supply noise.

3. High-Speed Material Selection for 112G PCBs

Standard FR4 materials are completely unusable at 28 GHz due to excessive dielectric loss (Dissipation Factor, Df) and unpredictable dielectric constants (Dk). 112G PCB design mandates the use of "Ultra-Low Loss" (ULL) or "Extreme Low Loss" laminates.

When selecting high speed PCB materials, engineers must look for Df values below 0.003 at 10 GHz to 30 GHz. Below is a comparison table of common material categories for AI servers.

Material Grade	Typical Df (at 10 GHz)	Typical Dk (at 10 GHz)	Example Commercial Materials	Suitability for 112G PAM4
Standard FR4	0.015 - 0.020	4.2 - 4.5	Isola 370HR, Shengyi S1000-2	Not Suitable
Mid-Loss	0.008 - 0.012	3.6 - 4.0	Panasonic Megtron 4, Isola I-Speed	Not Suitable (Max 10G/25G)
Very Low Loss	0.004 - 0.006	3.3 - 3.6	Panasonic Megtron 6, Isola Tachyon 100G	Marginal (Short trace lengths only)
Ultra / Extreme Low Loss	0.0015 - 0.003	3.0 - 3.4	Panasonic Megtron 8, Rogers RO4000, Shengyi S7439	Highly Recommended

For a deeper dive into laminates, see our complete guide on High-Speed PCB Materials for AI Servers.

4. PCB Stackup, Copper Roughness, and Skew

Beyond the resin system, the physical construction of the PCB directly impacts 112G Signal Integrity.

Copper Surface Roughness

At 28 GHz, the skin effect forces the high-frequency current to travel exclusively along the very outer surface (the "skin") of the copper trace. The skin depth (δ) can be calculated as:

δ = √( ρ / (π × f × μ) )

Where:

• ρ is the resistivity of copper (1.68 × 10^-8 Ω·m)
• f is the frequency (28 × 10⁹ Hz)
• μ is the magnetic permeability

At 28 GHz, the skin depth is approximately 0.39 μm. If the copper foil profile roughness (R_z) is larger than the skin depth, the signal must travel up and down the "mountains and valleys" of the copper, drastically increasing insertion loss. Therefore, 112G designs must utilize HVLP (Hyper Very Low Profile) or ultra-smooth copper foils with R_z < 1.0 μm.

Fiber Weave Effect and Glass Skew

PCB dielectrics are woven from glass bundles. If one trace of a differential pair routes over a glass bundle (higher Dk) while the other routes over the resin gap (lower Dk), the signals will travel at different speeds. This introduces intra-pair skew, converting differential signals into common-mode noise. To mitigate this in AI server motherboards, designers must use Mechanically Spread Glass (e.g., 1067, 1086, 1078 weaves) or route traces at a slight angle (e.g., 5° or 10°) relative to the weave.

5. Trace Routing Rules for 112G Signal Integrity

Effective 112G PAM4 PCB layout requires strict adherence to routing guidelines to minimize reflections and impedance discontinuities.

• Impedance Control: Differential pairs must tightly hold their target impedance (typically 85 Ω or 92 Ω for PCIe Gen5/Gen6 and high-speed Ethernet, depending on the spec). Tolerance should be controlled to ±5% or better. Read more in our PCIe Gen5 PCB Design Guidelines.
• Trace Geometry: Avoid 90-degree and even standard 45-degree bends if possible. Use curved/arc routing for all 112G traces to maintain a continuous cross-section.
• Intra-Pair Spacing: Maintain a loose coupling strategy. Wider trace-to-trace spacing reduces the skin-effect loss and minimizes the impact of manufacturing etching tolerances on differential impedance.
• Anti-Pad Dimensions: When traces pass over split planes, or when vias penetrate ground planes, carefully model the anti-pads in 3D EM simulation software (like Ansys HFSS) to avoid parasitic capacitance.

6. Via Optimization and Backdrilling

Vias are the biggest source of impedance discontinuities in high-speed PCB AI designs. When a signal transitions from layer 1 to layer 5 on a thick, high-layer-count board (often exceeding standard designs—see why AI GPU PCBs require 30+ layer HDI), the remaining copper barrel acts as an unterminated transmission line—a "stub".

This via stub creates a quarter-wave resonance null, filtering out high frequencies. The resonant frequency (f_res) is calculated as:

f_res = c / (4 × L_stub × √Dk_eff)

At 112 Gbps, a stub length of even 10 mils can destroy the signal eye. Therefore, Backdrilling (Controlled Depth Drilling) is absolutely mandatory. For 112G, the maximum allowable stub length after backdrilling is strictly ≤ 6 mils (0.15mm), pushing the limits of standard PCB fabrication capabilities.

Structure of an Optimized 112G Via

   [Trace In] ------------+
                          |
[GND Plane] --(Anti-pad)--+--(Anti-pad)--
                          |
[GND Plane] --(Anti-pad)--+--(Anti-pad)--
                          |
   [Trace Out] -----------+
                          |
                     (Backdrilled Air Gap)
                          |
[Bottom Layer] -----------x (Drilled out)

Furthermore, designers must add ground return vias adjacent to the signal vias (typically in a Ground-Signal-Signal-Ground configuration) to provide a continuous return path and contain electromagnetic fields.

7. Frequently Asked Questions (FAQ)

What is the maximum trace length for 112G PAM4 on a PCB?

It depends entirely on the PCB material and the SerDes (Serializer/Deserializer) drive strength and equalization capabilities (CTLE, DFE, FFE). Generally, even with Megtron 8, passive trace lengths are limited to 5 to 8 inches before active retimers or flyover cable assemblies are required.

Why can't I use NRZ for 112G instead of PAM4?

Transmitting 112 Gbps using NRZ would require a Nyquist frequency of 56 GHz. At 56 GHz, the insertion loss of copper traces and the parasitic capacitance of vias and connectors are insurmountable for standard server form factors. PAM4 halves the required bandwidth to 28 GHz.

How does 112G PAM4 relate to 800G Ethernet?

800G Ethernet typically consists of 8 parallel lanes of 112G PAM4 signals (8 × 112G = 896G raw, 800G effective data rate). Therefore, designing an 800G switch board means routing dozens of 112G PAM4 lanes simultaneously.

8. Conclusion

Mastering 112g pam4 pcb design is non-negotiable for engineers building the infrastructure of the AI era. Success requires a holistic approach: specifying ultra-low loss materials with HVLP copper, running exhaustive 3D electromagnetic simulations, utilizing mechanically spread glass, and collaborating closely with a highly capable manufacturer with advanced PCB manufacturing capabilities that can execute backdrilling and impedance control with microscopic precision.

Furthermore, once the bare boards are fabricated, these complex designs demand equally precise PCB assembly capabilities to reliably mount high-density BGA packages and SerDes retimers. Always run a comprehensive Design for Manufacturability (DFM) check to ensure your tight tolerances can be achieved in mass production.

As you move your AI accelerator designs from schematic to layout, remember that the margin for error at 28 GHz is practically zero. You can verify your layout files using our Free Online Gerber Viewer to spot any obvious via or trace geometry issues before prototyping.

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