PCIe Gen5 PCB Design Guidelines: Impedance, Loss Budget & Via Optimization

Introduction

PCIe Gen5 (PCIe 5.0) doubles the per-lane data rate of Gen4 from 16 GT/s to 32 GT/s, delivering approximately 128 GB/s of bandwidth across a ×16 link. This doubling in speed comes with a corresponding increase in the difficulty of the PCB design problem: the Nyquist frequency of a Gen5 lane is 16 GHz, compared to 8 GHz for Gen4, and dielectric losses, copper conductor losses, via reflections, and crosstalk all scale unfavorably with frequency.

In AI server baseboards, PCIe Gen5 is the standard host interface connecting CPUs to GPU accelerators. The H100 SXM5, AMD MI300X, and Intel Gaudi 3 all use PCIe Gen5 ×16 as their primary host bus. Every AI server PCB built for these accelerators must implement one or more PCIe Gen5 channels correctly. Getting the design wrong results in link training failures, reduced effective throughput due to FEC overhead, or outright inability to train the PCIe link at Gen5 speeds—forcing fallback to Gen4 and halving the available CPU-to-GPU bandwidth.

This article provides a complete PCIe Gen5 PCB design guide, covering channel loss budget, impedance control, laminate selection, via optimization, routing rules, and compliance testing. Where relevant, the guidelines are placed in the context of AI server baseboard design.

1. Table of Contents
2. Introduction
3. PCIe Gen5 Basics: Speed, Encoding, and Signal Characteristics
4. Channel Loss Budget: The Central Design Constraint
5. Differential Impedance: Target, Tolerance, and Control
6. Laminate Selection for PCIe Gen5
7. Via Optimization: The Most Critical Design Step
8. Trace Routing Rules
9. Connector and Package Launch Design
10. Recommended Layer Stackup for PCIe Gen5
11. Simulation and Pre-Layout Channel Budgeting
12. Compliance Testing
13. PCIe Gen5 vs Gen4: What Changes in the PCB Design
14. PCIe Gen5 in AI Server Baseboards
15. FAQ

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PCIe Gen5 Basics: Speed, Encoding, and Signal Characteristics

Parameter	PCIe Gen3	PCIe Gen4	PCIe Gen5
Line rate (GT/s)	8	16	32
Encoding	128b/130b NRZ	128b/130b NRZ	128b/130b NRZ
Effective bandwidth per lane (each direction)	~1 GB/s	~2 GB/s	~4 GB/s
×16 link bandwidth (bidirectional)	~32 GB/s	~64 GB/s	~128 GB/s
Nyquist frequency	4 GHz	8 GHz	16 GHz
UI (Unit Interval)	125 ps	62.5 ps	31.25 ps
Differential impedance	85 Ω ± 15%	85 Ω ± 15%	85 Ω ± 10%
Maximum channel insertion loss	< 20 dB at 4 GHz	< 28 dB at 8 GHz	< 28 dB at 16 GHz
FEC	No	No	Yes (mandatory)

PCIe Gen5 retains NRZ (Non-Return-to-Zero) signaling, unlike the PAM4 modulation used in PCIe Gen6. This is significant: NRZ Gen5 has better noise margins than PAM4 at the same data rate, which is why the Gen5 channel insertion loss limit (28 dB at 16 GHz) is achievable with careful PCB design using commercially available materials, whereas Gen6 PAM4 at the same frequency imposes a far tighter effective noise budget per bit.

Forward Error Correction (FEC) is mandatory in PCIe Gen5. FEC can correct burst errors that would cause link failures in Gen4, but it does so at the cost of approximately 2–4 ns of additional latency per direction. FEC does not substitute for good channel design—excessive raw bit error rate before FEC correction degrades throughput and increases FEC correction overhead even when the link remains up.

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Channel Loss Budget: The Central Design Constraint

The PCIe Gen5 channel loss budget is the envelope within which the complete signal path from transmitter output pad to receiver input pad must fit. The budget is defined in the PCIe Base Specification 5.0 and covers four loss mechanisms.

Insertion Loss (IL)

Insertion loss is the ratio of signal power delivered to the load versus power available from the source, expressed in decibels (dB). For PCIe Gen5, the maximum allowed channel insertion loss is:

• 28 dB at 16 GHz (Nyquist) for the worst-case compliant channel
• This includes PCB trace loss, via loss, connector loss, and package loss
• The specification is measured from the transmitter package pin reference plane to the receiver package pin reference plane

Insertion loss accumulates from multiple contributors along the channel. A representative budget breakdown for a PCIe Gen5 channel on an AI server baseboard:

Loss Contributor	Typical Loss at 16 GHz	Notes
PCB trace (dielectric loss)	10–18 dB	Dominant contributor; depends on trace length, laminate Df, and copper roughness
PCB trace (conductor loss)	3–8 dB	Skin-effect loss; reduced by smooth (LP/VLP) copper foil
Via structures (launch + transition vias)	1–4 dB	Anti-pad geometry, stub resonance (if not backdrilled), via wall roughness
Connector loss (if present)	0.5–3 dB	PCIe slot edge connector, press-fit connectors; depends on connector quality
Package and die pad launch	1–2 dB	Package substrate routing and ball/pad launch; specified by component vendor
Total budget	< 28 dB	Must not exceed specification limit

On a 300 mm long PCIe Gen5 trace in standard FR4, dielectric loss alone at 16 GHz exceeds 28 dB—the total channel budget. This is why standard FR4 cannot be used for PCIe Gen5 signal routing layers.

Return Loss (RL)

Return loss measures the impedance discontinuities in the channel. The PCIe Gen5 specification requires:

• Return loss < −9 dB at frequencies from 50 MHz to 16 GHz for the full channel
• Differential to common mode conversion (Sdc21) < −35 dB across the same frequency range

The primary sources of return loss in a PCIe Gen5 channel are via transitions (impedance discontinuity at the pad launch into the via barrel), connector transitions, and any trace width changes introduced by routing topology decisions or manufacturing variation. Each return loss source also reflects energy back toward the transmitter, which appears as intersymbol interference (ISI) at the receiver and degrades the eye opening.

Crosstalk (NEXT and FEXT)

Crosstalk specifications for PCIe Gen5:

• Near-end crosstalk (NEXT): < −35 dB integrated (ICN) across the relevant frequency range
• Far-end crosstalk (FEXT): < −26 dB integrated (ICF) across the relevant frequency range

These limits apply to the crosstalk coupling between any two adjacent PCIe lanes in the same direction. At 16 GHz, crosstalk coupling increases relative to Gen4 at 8 GHz, requiring larger lane-to-lane spacing or more aggressive shielding (ground traces between lanes, or routing on dedicated layers with ground planes above and below).

Loss Budget Allocation Table

The following table shows how the 28 dB budget is typically allocated for different PCIe Gen5 channel topologies on AI server baseboards:

Channel Topology	Trace Length	Trace Loss Allocation	Via + Connector Allocation	Margin
CPU to GPU (no connector)	150–200 mm	18–22 dB	3–5 dB	1–7 dB
CPU to GPU (with PCIe slot/riser)	200–300 mm	22–26 dB	3–6 dB	Tight; requires low-loss material
CPU to PCIe switch then to device	300–450 mm total	24–28 dB	4–8 dB	Requires retimer or low-loss premium material

Channels that exceed the 28 dB budget require a PCIe retimer (a signal conditioning chip that regenerates the PCIe signal partway through the channel) to meet the specification. Retimers add cost, board area, power, and latency; good channel design avoids the need for retimers where possible.

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Differential Impedance: Target, Tolerance, and Control

Target Value and Tolerance

PCIe Gen5 specifies 85 Ω ± 10% differential impedance for the PCB trace (tighter than the Gen3/Gen4 ± 15% tolerance). The narrowed tolerance reflects the sensitivity of the Gen5 channel loss budget to impedance discontinuities: a ± 15% impedance excursion produces a reflection coefficient of approximately −20 dB, which is acceptable at Gen4 frequencies but too large at Gen5 given the tighter return loss budget.

The 85 Ω differential impedance target applies to edge-coupled differential pairs (the standard orientation for PCIe traces). This corresponds to a single-ended impedance of approximately 45–48 Ω per conductor, with the coupling between the two conductors providing the balance of the differential impedance.

Trace Geometry for 85 Ω Differential Impedance

The trace width and spacing required to achieve 85 Ω differential impedance depend on the dielectric constant (Dk) of the laminate and the dielectric thickness between the trace layer and the adjacent reference plane. Representative geometries for common laminate materials:

Laminate	Dk (at 10 GHz)	Dielectric Thickness (μm)	Trace Width (μm)	Trace Spacing (μm)	Resulting Zdiff
Standard FR4	4.5	100	90	90	~85 Ω
Panasonic Megtron 6	3.6	100	105	90	~85 Ω
Panasonic Megtron 6E	3.4	100	110	90	~85 Ω
Isola Tachyon 100G	3.6	100	105	90	~85 Ω
Panasonic Megtron 7	3.4	100	112	90	~85 Ω

Note that lower Dk materials (Megtron 6E, Megtron 7) require slightly wider traces to achieve the same 85 Ω target compared to higher Dk materials at the same dielectric thickness. Wider traces have lower conductor resistance, which partially compensates for the lower dielectric loss of the premium material.

All impedance values above are approximate and must be verified by the fabricator using their actual process parameters. Fabricators should provide impedance test coupon data from the same production run to verify that as-built impedance is within ± 10% of the 85 Ω target.

Sources of Impedance Variation

The primary contributors to impedance variation in PCIe Gen5 traces are:

• Trace width variation: Etching non-uniformity introduces ± 5–10 μm trace width variation across the panel; a 10 μm variation on a 100 μm trace represents a 10% width deviation, which directly translates to approximately 3–5% impedance deviation
• Dielectric thickness variation: Prepreg thickness after pressing varies ± 3–5% from nominal due to resin flow non-uniformity; a 5% thinner dielectric increases impedance by approximately 2–3%
• Dk variation: Low-loss laminates have tighter Dk variation than standard FR4 (± 0.1 vs ± 0.3), contributing to better impedance uniformity; this is one reason premium laminates are used even where the dielectric loss would be acceptable with a lower-grade material
• Trace neck-down at vias: Via anti-pad clearances force trace width reduction as traces exit the via pad; the neck-down creates a local impedance spike that contributes to return loss

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Laminate Selection for PCIe Gen5

Dielectric Loss at 16 GHz

Dielectric loss is proportional to frequency × Df (dissipation factor). At 16 GHz (PCIe Gen5 Nyquist), the dielectric loss per unit length is approximately 2× the loss at 8 GHz (PCIe Gen4 Nyquist) for the same material. This frequency scaling makes laminate Df selection critical:

• Standard FR4 (Df ~0.020): at 16 GHz, FR4 generates approximately 1.5–2.0 dB/cm of insertion loss—a 150 mm trace would consume 22–30 dB of the 28 dB budget in dielectric loss alone, leaving no margin for via and connector losses
• Megtron 6 (Df ~0.004): approximately 0.4–0.5 dB/cm at 16 GHz; a 150 mm trace consumes 6–8 dB, leaving adequate margin for via and connector losses in a direct CPU-to-GPU channel
• Megtron 6E / Tachyon 100G (Df ~0.002–0.003): approximately 0.25–0.35 dB/cm at 16 GHz; preferred for longer channels or channels with multiple via transitions and connectors

Copper Foil Grade

Conductor (skin-effect) loss is the second significant loss mechanism at 16 GHz. Skin effect concentrates current flow in a thin surface layer of the conductor; the rougher the conductor surface, the more the effective current path length increases, raising resistance and loss.

• Standard ED copper (Rz ~6–10 μm surface roughness): Acceptable for Gen4; at Gen5 frequencies, roughness-induced loss adds 1–3 dB to the conductor loss relative to smooth copper on a 150 mm trace
• Low-profile (LP) copper (Rz ~2–4 μm): Adequate for many PCIe Gen5 designs; recommended minimum for Gen5 signal layers
• Very-low-profile (VLP) copper (Rz < 2 μm): Best practice for PCIe Gen5 on premium laminates; reduces conductor loss by 0.5–1.5 dB on a 150 mm trace compared to standard ED copper; mandatory for NVLink 4.0 and NVLink 5.0 layers (see What Is NVLink? How NVIDIA's High-Speed GPU Interconnect Shapes PCB Routing)

Material Comparison Table

Laminate	Df (10 GHz)	Dk (10 GHz)	PCIe Gen5 Suitability	Recommended Channel Length
Standard FR4	~0.020	~4.5	Not suitable	< 50 mm only (marginal even then)
Isola FR408HR	~0.010	~3.7	Marginal; short channels only	< 100 mm with careful via design
Panasonic Megtron 6	~0.004	~3.6	Good for direct on-board channels	Up to 200 mm (no connector)
Isola Tachyon 100G	~0.0021	~3.6	Excellent	Up to 250 mm; suitable with one connector
Panasonic Megtron 6E	~0.0024	~3.4	Excellent	Up to 250 mm; suitable with one connector
Panasonic Megtron 7	~0.0020	~3.4	Best-in-class; overspec for Gen5 alone	Required for NVLink 5.0 co-routed boards

For AI server baseboards where PCIe Gen5 traces share a stackup with NVLink 4.0 or NVLink 5.0 routing, the laminate selection is driven by the NVLink requirement (Megtron 6E or Megtron 7), and PCIe Gen5 performance benefits automatically from the better material. See the AI Accelerator PCB Design Guide for a full material selection framework for AI server boards.

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Via Optimization: The Most Critical Design Step

Via optimization is arguably the single most impactful PCB design step for PCIe Gen5 performance. Via structures introduce impedance discontinuities (reflections) and resonances (insertion loss spikes) at frequencies that fall directly within the Gen5 signal band. Getting via design wrong can cost 3–8 dB of channel margin—enough to push a borderline channel over the 28 dB insertion loss limit.

The Via Stub Problem

A through-hole via that connects a signal from layer L1 to layer L5 in a 12-layer board has an unused section from layer L5 to layer L12—the stub. This stub is an unterminated transmission line segment. Its electrical length depends on the stub physical length and the propagation velocity in the board material.

The stub resonates at a frequency where its length equals a quarter wavelength (λ/4). At resonance, the stub presents a short circuit at the via junction, creating a null in the insertion loss response. For a 2 mm stub in Megtron 6 (propagation velocity ~17 cm/ns):

f_null = v_p / (4 × L_stub) = 170 mm/ns / (4 × 2 mm) = 21.25 GHz

A 2 mm stub creates a null at 21.25 GHz—above the PCIe Gen5 Nyquist of 16 GHz, so the 28 dB budget at 16 GHz is not directly affected. However, the skirt of the resonance extends below the null frequency, and the resulting insertion loss increase at 14–16 GHz can consume 1–3 dB of the budget.

For a 1 mm stub:

f_null = 170 / (4 × 1) = 42.5 GHz (well clear of Gen5 band)

Reducing stub length to < 1 mm (approximately 40 mils) brings the stub resonance frequency to > 40 GHz, safely above the Gen5 signal band. At stubs below this length, the impact on Gen5 channel loss is typically < 0.5 dB.

Backdrilling: Removing the Stub

Backdrilling drills from the opposite board face to remove the stub portion of the via, leaving only the functional barrel section. For PCIe Gen5:

• Target stub length after backdrilling: < 10 mils (254 μm) for PCIe Gen5; this brings the stub resonance above 40 GHz and its impact on the Gen5 channel to < 0.5 dB
• Backdrill diameter: Typically 0.2–0.4 mm larger than the original drill diameter, to ensure complete removal of the plated stub including the barrel wall
• Depth accuracy: ± 50 μm; requires CNC machines with depth feedback; drill depth files should be generated from measured as-built stackup thickness for each production panel
• When backdrilling is required: On any through-hole via carrying PCIe Gen5 signals where the stub length (board thickness minus signal connection depth) exceeds approximately 1 mm (40 mils); for most PCIe Gen5 AI server boards with 3–5 mm total thickness, backdrilling is required on virtually all signal vias

Via Pad and Anti-Pad Geometry

The via pad (the annular copper ring around the drill hole) and anti-pad (the clearance hole in adjacent copper planes) geometry significantly affect the via's contribution to channel loss and return loss:

• Pad diameter: Minimum pad diameter is drill diameter + 2 × minimum annular ring (≥ 50 μm); larger pads provide better drilling registration margin but increase the effective capacitance of the via transition, causing a local impedance dip below 85 Ω
• Anti-pad diameter: Larger anti-pads reduce the shunt capacitance of the via, raising the local impedance back toward 85 Ω; however, excessively large anti-pads disrupt the reference plane, degrading impedance uniformity in the adjacent trace. Optimal anti-pad diameter is typically 0.3–0.5 mm larger than the drill diameter for a 0.25 mm drill
• Differential via pair geometry: For differential pairs, the two vias should be placed as close together as permitted (typically 0.8–1.2 mm center-to-center), and their anti-pads should be merged into a single oval or dog-bone shape to minimize reference plane disruption and maintain differential mode propagation through the via transition
• Ground stitching vias: Ground vias placed in a regular array around signal via pairs provide a controlled return current path and reduce the inductance of the via transition; spacing of ground vias at 1–2 mm from signal vias on each side is standard practice for Gen5

Blind and Buried Via Alternatives

Blind vias (connecting an outer layer to an inner layer, not passing through the full board thickness) eliminate stubs entirely for the layers they connect. For PCIe Gen5 in AI server boards using HDI technology:

• Laser-drilled blind microvias (75–150 μm diameter) can connect PCIe Gen5 traces from outer build-up layers to inner signal routing layers without creating stubs; this eliminates the need for backdrilling on those via transitions
• The trade-off is manufacturing cost: laser-drilled build-up vias require sequential lamination and add cost and lead time compared to standard through-hole vias with backdrilling
• For the most loss-sensitive PCIe Gen5 channels (maximum trace length, multiple layer transitions), replacing through-hole vias with blind microvia transitions on critical signal paths is the highest-performance option

Layer Transition Design

Each time a PCIe Gen5 trace transitions from one routing layer to another (to escape a BGA, avoid an obstruction, or change routing direction), the via structure introduces discontinuities. Best practices:

• Minimize the total number of layer transitions in the channel; each transition costs 0.3–1.0 dB in insertion loss and contributes to return loss degradation
• Keep the transition via as close to the transmitter and receiver package launches as possible; transitions early or late in the channel, where the trace has less time to accumulate loss, have proportionally less impact on the total budget
• Maintain the same differential pair orientation (horizontal or vertical coupling between the two traces) through the via transition; asymmetric via structures that swap the pair orientation introduce mode conversion (differential to common mode), degrading signal quality

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Trace Routing Rules

Intra-Pair Skew

Intra-pair skew is the difference in electrical length between the positive (P) and negative (N) conductors of a differential pair. Unequal lengths cause the two signals to arrive at the receiver at different times, converting differential mode signal into common mode noise. PCIe Gen5 requires:

• Intra-pair skew < 1.5 ps within each differential pair segment between vias
• Across the full channel, intra-pair skew should be < 5 ps to stay within the receiver's common mode rejection capability
• Serpentine length matching structures are used to equalize P and N trace lengths; these must be placed within the segment where the skew originates and should use gentle meandering (meander pitch ≥ 3× trace width to avoid inductive coupling between adjacent segments)

Inter-Pair Skew and Length Matching

PCIe Gen5 uses 8b/10b and 128b/130b encoded data that is striped across multiple lanes in a link. The PCIe specification accommodates inter-lane skew through link training, but excessive inter-lane skew increases training time and can cause training failures on marginal channels:

• Inter-pair (lane-to-lane) skew should be < 200 ps within the PCB for PCIe Gen5; this is relatively relaxed compared to intra-pair skew and is easily met by routing all lanes on the same layer or keeping length differences between lanes < 30–40 mm
• For AI server baseboards where all PCIe lanes from a CPU port connect to a single GPU or accelerator, routing all lanes at the same board-level length with < 5 mm variation is straightforward design practice

Spacing and Crosstalk

PCIe Gen5 lane-to-lane crosstalk must stay below the ICN and ICF limits. Recommended spacing rules:

• Between differential pairs (edge-to-edge): Minimum 3× trace width (3W rule); at 100 μm trace width, minimum 300 μm edge-to-edge spacing between adjacent differential pairs
• Between PCIe TX and RX directions: TX and RX traces run in opposite directions on the same link; while these are inherently orthogonal in differential mode, placing TX and RX traces on different layers separated by a ground plane provides the best crosstalk isolation and is best practice for Gen5
• Between PCIe and NVLink traces: On AI server baseboards where PCIe Gen5 and NVLink 4.0 traces coexist, maintain ≥ 5× trace width separation between the two signal groups, or route them on separate dedicated layers; NVLink operates at the same or higher frequency than Gen5 and will couple energy into PCIe traces if routed in parallel

Reference Plane Continuity

The reference plane adjacent to a PCIe Gen5 routing layer must be continuous and unbroken beneath all active signal traces:

• No power plane splits, connector cutouts, or large via anti-pad arrays should be present directly beneath PCIe Gen5 traces
• Where the reference plane must be interrupted (at a connector footprint, for example), route PCIe traces to avoid the interrupt zone; if unavoidable, place stitching ground vias on either side of the interrupt to provide a continuous return current path
• Changing reference planes during a layer transition (e.g., routing a trace from a layer referenced to ground plane A to a layer referenced to ground plane B) requires a ground stitching via directly adjacent to the signal via to provide a low-impedance return path for the common mode currents; without this via, the return path must travel a long distance through the board, creating a loop that radiates and receives EMI

Bends and Corners

At PCIe Gen5 frequencies, right-angle corners in traces cause excess capacitance and minor impedance discontinuities. Best practice:

• Use 45° chamfered bends or gentle arcs; avoid 90° corners on all PCIe Gen5 traces
• For differential pairs, both conductors of the pair must bend simultaneously (mitered bends for each conductor), maintaining equal length through the bend
• The impedance impact of a 45° chamfered corner at 16 GHz is small (< 0.2 dB) for typical trace widths; the primary reason to avoid sharp corners is EMI compliance rather than channel loss

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Connector and Package Launch Design

The transition from PCB trace to component package (GPU, CPU, or PCIe switch) and to connectors (PCIe slot, press-fit, or board-to-board) are the highest-risk impedance discontinuities in the PCIe Gen5 channel. Design guidelines:

• Package launch via: The via that connects the PCB trace to the BGA package ball is the first and last via in the channel; its impedance must be controlled by selecting appropriate pad diameter and anti-pad geometry; simulation of the package launch via using the component vendor's IBIS-AMI or s-parameter model is strongly recommended
• PCIe slot connector: For standard PCIe add-in card slots, the slot connector's insertion loss (typically 0.5–2 dB at 16 GHz) must be included in the channel loss budget; connector vendor s-parameter models are required for accurate budget modeling
• PCB-to-board connector: Press-fit or SMT board-to-board connectors for PCIe Gen5 must be rated to at least 16 GHz; high-speed press-fit connectors from Amphenol, TE Connectivity, and Molex specify insertion loss at 16 GHz in their datasheets and should be selected with < 2 dB at 16 GHz per connector pair

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Recommended Layer Stackup for PCIe Gen5

For a standalone PCIe Gen5 board (e.g., a PCIe add-in card or a smaller inference board), a practical 12–16 layer stackup for PCIe Gen5:

Layer	Function	Material	Notes
L1	SMT pads; short low-speed signals	Core prepreg	ENIG surface finish
L2	Ground reference plane	Core	Solid pour; no splits under PCIe traces
L3	PCIe Gen5 TX signal routing (horizontal)	Megtron 6E or equivalent	VLP copper; 85 Ω differential; backdrilled vias
L4	Ground reference plane	Core	Separates TX and RX layers
L5	PCIe Gen5 RX signal routing (vertical)	Megtron 6E or equivalent	VLP copper; opposite direction to TX
L6	Ground reference plane	Core
L7	Power plane (VCC)	Standard laminate	1–2 oz copper
L8	Ground plane (power return)	Standard laminate
L9	Low-speed signal routing	Standard laminate	Management, I2C, UART
L10	Ground reference	Standard laminate
L11	Additional power plane	Standard laminate	1.8 V, 3.3 V auxiliary
L12	SMT pads; bottom-side components	Core prepreg	ENIG surface finish

For AI server baseboards where PCIe Gen5 shares the stackup with NVLink routing (see Why AI GPUs Require 30+ Layer HDI PCBs), the PCIe Gen5 signal layers are additional layers within the full 20–32+ layer stackup, and the laminate material selection is driven by the NVLink requirement.

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Simulation and Pre-Layout Channel Budgeting

Pre-layout simulation is strongly recommended for PCIe Gen5 channels, particularly those with multiple layer transitions, connectors, or trace lengths approaching the 28 dB budget limit. The simulation workflow:

1. Stackup simulation: Use a 2D field solver (Polar Si9000, Ansys SIwave, Cadence Clarity) to simulate the differential impedance and per-unit-length insertion loss for the proposed trace geometry and laminate; verify that the impedance is within ± 10% of 85 Ω and that the per-unit-length loss at 16 GHz is within budget
2. Via simulation: Build a 3D model of the via transition (pad geometry, anti-pad, stub length, ground stitching vias) and simulate S-parameters to quantify via insertion loss and return loss contribution; adjust anti-pad geometry or stub length to meet the RL budget
3. Full channel simulation: Cascade the trace, via, connector, and package launch S-parameter models into a complete channel simulation; verify that the composite insertion loss at 16 GHz is below 28 dB and that the return loss and crosstalk specifications are met
4. Statistical worst-case analysis: Monte Carlo simulation across manufacturing tolerances (trace width ± 10 μm, dielectric thickness ± 5%, Dk ± 0.1) to verify that the channel meets specification even under worst-case process variation

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Compliance Testing

PCIe Gen5 compliance testing verifies that devices and channels meet the Base Specification requirements. For PCB design, the relevant tests are:

• Insertion loss measurement: VNA (Vector Network Analyzer) measurement of S₂₁ (insertion loss) and S₁₁ (return loss) on channel coupons fabricated alongside the production boards; coupon trace length is typically 20–30 cm with access launches at each end
• Eye diagram: Time domain measurement of the signal eye opening at the receiver after the PCB channel; eye mask compliance verifies that the channel does not close the eye below the minimum specification
• BERT (Bit Error Rate Tester) testing: Measures the raw bit error rate of the PCIe link at Gen5 speed before FEC; target pre-FEC BER is typically < 10⁻⁴ for a compliant channel; post-FEC BER specification is < 10⁻¹²
• PCI-SIG compliance workshop: For PCIe add-in cards and host platforms intended for broad market deployment, official PCI-SIG compliance testing at an authorized test laboratory is required; AI server boards sold to hyperscale customers typically undergo internal compliance testing against the Base Specification rather than formal PCI-SIG certification

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PCIe Gen5 vs Gen4: What Changes in the PCB Design

Design Parameter	PCIe Gen4	PCIe Gen5	Impact
Nyquist frequency	8 GHz	16 GHz	All frequency-dependent losses roughly double
Differential impedance tolerance	85 Ω ± 15%	85 Ω ± 10%	Tighter manufacturing tolerance required
Max channel insertion loss	< 28 dB at 8 GHz	< 28 dB at 16 GHz	Same limit, harder to achieve at 2× frequency
FEC	Not required	Mandatory	Adds latency; does not replace good channel design
Laminate minimum	Megtron 6 (Df ~0.004)	Megtron 6E or Tachyon 100G (Df ~0.002–0.003)	Higher material cost on Gen5 signal layers
Copper foil grade	LP acceptable	LP minimum; VLP recommended	Marginally higher fabrication cost
Via backdrilling	Recommended; not always required	Required on boards > 2 mm thick	Additional fabrication step; adds lead time and cost
Crosstalk spacing	2W rule acceptable	3W rule strongly recommended	Slightly wider routing channels required
Retimer requirement	Optional for long channels	May be required for channels > 250–300 mm	Additional cost and complexity if retimer needed

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PCIe Gen5 in AI Server Baseboards

In AI server baseboards for H100, MI300X, and Gaudi 3, PCIe Gen5 is the host interface connecting the CPU to each GPU or accelerator. The PCIe Gen5 design challenges on these boards are compounded by several factors not present in a standalone PCIe add-in card design:

• Multiple parallel PCIe channels: A DGX H100 baseboard routes PCIe Gen5 ×16 channels from two host CPUs to eight GPU SXM5 sockets, plus additional PCIe connections to NIC and management components; the total number of PCIe Gen5 lanes on the baseboard exceeds 256; routing them while avoiding crosstalk with the adjacent NVLink 4.0 fabric requires careful layer assignment and spacing discipline
• Shared stackup with NVLink: PCIe Gen5 signal layers coexist in the same stackup as NVLink 4.0 routing layers on the H100 baseboard; the laminate must meet NVLink requirements (Megtron 6E, Df ≤ 0.003), which also more than satisfies PCIe Gen5 requirements—so the material choice is not a compromise
• Long trace lengths: In an 8-GPU baseboard, the PCIe channel from a centrally mounted CPU to a GPU at the board edge may be 200–300 mm; at these lengths, careful loss budget management and potentially a PCIe retimer are required to meet the 28 dB specification
• B200 and PCIe Gen6: The B200 Blackwell GPU uses PCIe Gen6 (PAM4, 64 GT/s per lane) rather than Gen5; the PCB design challenges for Gen6 are significantly more demanding. See NVIDIA Blackwell Architecture Explained for PCIe Gen6 PCB design requirements

For a complete treatment of AI server baseboard PCB design across all high-speed interfaces, see the AI Accelerator PCB Design Guide and A100 vs H100: PCB Stack Differences Explained.

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FAQ

Can standard FR4 be used for PCIe Gen5 PCB design?
No, for any practical channel length. Standard FR4 (Df ~0.020) generates approximately 1.5–2.0 dB/cm of insertion loss at 16 GHz. A 150 mm channel trace would contribute 22–30 dB of dielectric loss alone, consuming or exceeding the entire 28 dB channel budget before via and connector losses are added. PCIe Gen5 signal routing layers require low-loss laminates with Df ≤ 0.005 at 10 GHz—at minimum Megtron 6, and preferably Megtron 6E or Tachyon 100G for channels longer than 150 mm.

Is backdrilling always required for PCIe Gen5?
On boards thicker than approximately 1.5–2 mm, yes. The stub from a through-hole via in a 3–5 mm thick board (typical for multi-layer AI server PCBs) is long enough to create stub resonances whose skirts degrade the channel insertion loss at 16 GHz. For boards thinner than 1.5 mm (e.g., thin PCIe add-in cards), the stub is short enough that its resonance frequency is above 40 GHz and its impact on Gen5 channel performance is negligible. In practice, all AI server baseboards are thick enough to require backdrilling on PCIe Gen5 signal vias.

What is the maximum PCIe Gen5 trace length without a retimer?
It depends on the laminate material and via design. With Megtron 6E (Df ~0.0024) and VLP copper, well-designed vias (< 1 mm stub after backdrilling), and no connectors, a trace length of approximately 200–250 mm is achievable within the 28 dB budget. Adding a PCIe slot connector reduces this to approximately 150–200 mm. Beyond these lengths, a retimer is typically required to regenerate the signal before the next stage of the channel.

Does PCIe Gen5 require a different connector than Gen4?
The PCIe physical slot connector (CEM connector) is backward compatible across generations—a PCIe Gen5 card will physically fit in a Gen4 slot. However, PCIe Gen5 signal integrity requirements demand that connectors used at 32 GT/s meet tighter insertion loss and return loss specifications than many Gen4-era connectors. For PCB-to-PCB applications (press-fit or SMT connectors between the baseboard and a riser or switch card), connectors must be specifically rated for 32 GT/s / 16 GHz operation; not all Gen4-qualified connectors meet this requirement.

How does PCIe Gen5 FEC affect system design?
FEC adds approximately 2–4 ns of latency per PCIe direction. For most AI workloads, where the GPU-to-CPU PCIe channel is used for relatively infrequent data transfers (model loading, checkpoint writing), this latency is not performance-critical. FEC also reduces the sensitivity of the PCIe link to individual bit errors, providing some margin against marginal channel performance. However, FEC increases the overhead of error correction under high bit error rate conditions, potentially reducing effective throughput on consistently poor channels. Good channel design targets a pre-FEC BER < 10⁻⁴, leaving adequate FEC headroom without throughput degradation.

What test equipment is needed to verify a PCIe Gen5 channel?
Comprehensive PCIe Gen5 channel verification requires: a VNA (Vector Network Analyzer) capable of measurements to at least 20 GHz for S-parameter measurement of channel coupons; a high-speed oscilloscope (100 GHz+ analog bandwidth, or 50 GHz minimum) for eye diagram measurement; and a BERT (Bit Error Rate Tester) with a PCIe Gen5-capable pattern generator and error detector for link-level BER testing. For AI server board development programs, all three instrument types are typically used at different stages of the design verification process.

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Need to Manufacture AI Server PCBs?

PCIe Gen5 PCB design requires the right laminate materials, precise impedance control, controlled-depth backdrilling, and manufacturing expertise to deliver channels that consistently pass compliance testing. NextPCB provides low-loss laminate processing, ± 5% impedance control, backdrilling, HDI, and complete PCBA services for AI server and data center PCB programs.

 

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