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The printed circuit board laminate used in an AI server GPU baseboard is not chosen for its fire rating or dimensional stability alone. It is chosen primarily for how little signal energy it wastes at frequencies between 10 and 25 GHz—the range that NVLink 4.0, NVLink 5.0, PCIe Gen5, and PCIe Gen6 signals occupy when operating at full speed.
Material selection is one of the earliest and most consequential decisions in AI server PCB design. Choose a laminate with too high a dissipation factor and the channel insertion loss exceeds specification before the via and connector losses are even added. Choose a material that is unnecessarily low-loss and the board cost escalates without a corresponding performance benefit. Choose a material that the fabricator cannot reliably process and prototype yield drops, extending program timelines.
This article covers every major low-loss laminate family used in AI server PCBs today—Panasonic Megtron, Isola Tachyon, Rogers, and others—explaining the key properties, trade-offs, and practical selection criteria for each, from H100-era boards through B200 and NVLink 5.0 designs.
Standard FR4 is an epoxy-glass laminate that has served as the default PCB material for decades. It is cost-effective, mechanically robust, easy to process, and entirely adequate for signals below approximately 5 GHz. Above that frequency, two properties make it unsuitable for AI server applications.
The first is its dissipation factor (Df), also called the loss tangent. FR4 has a Df of approximately 0.018–0.025 at 10 GHz. Df is directly proportional to the dielectric insertion loss per unit length of a transmission line. At 10 GHz on a typical 100 μm dielectric thickness microstrip, standard FR4 generates approximately 1.5–2.0 dB per centimeter of insertion loss. An NVLink 4.0 signal running 15 cm from a GPU package to an NVSwitch chip would suffer 22–30 dB of dielectric loss alone—already consuming or exceeding the total channel budget before any via or connector losses are added.
The second is the variability of its dielectric constant (Dk). Standard FR4 is a woven glass-epoxy composite, and the Dk varies depending on the weave angle, resin content, and moisture absorption of the specific panel. This variability translates directly into impedance variation across the board, making it difficult to hold the ± 5% differential impedance tolerance required by NVLink 4.0 and NVLink 5.0 on a standard FR4 process.
Low-loss laminates solve both problems: they are formulated with resin systems that have intrinsically lower molecular polarizability (lower Df at high frequency) and more uniform Dk across processing conditions.
Three material parameters dominate the selection decision for AI server PCB laminates.
Dielectric constant (Dk, also called relative permittivity εr): Dk determines the propagation velocity of a signal in the material and therefore the physical trace length required to achieve a given electrical delay. Lower Dk means higher propagation velocity and slightly lower per-unit-length capacitance, which allows slightly wider traces for the same impedance target. For AI server boards, Dk values between 3.3 and 3.8 at 10 GHz are typical among low-loss laminates. Dk uniformity (how consistent it is across a panel and across production lots) affects impedance control more than the absolute value.
Dissipation factor (Df, also called loss tangent tanδ): Df is the ratio of energy dissipated as heat to energy stored in the dielectric per cycle. Dielectric insertion loss per unit length scales linearly with both frequency and Df. For a stripline in a typical AI server stackup, the dielectric loss in dB per centimeter is approximately:
ILdiel (dB/cm) ≈ 27.3 × Df × f(GHz) × √Dk / c
where c is the speed of light. At 10 GHz and Dk = 3.6, moving from FR4 (Df = 0.020) to Megtron 7 (Df = 0.002) reduces dielectric loss per centimeter by a factor of 10. For a 15 cm NVLink 5.0 channel, this difference is approximately 15 dB—the difference between a compliant and a non-compliant channel.
Copper foil surface roughness: The copper foil bonded to the laminate surface affects conductor (skin-effect) loss at high frequencies. Current at high frequency flows in a thin skin depth at the conductor surface; a rougher surface increases the effective path length of current flow, raising resistance and loss. Foil roughness is characterized by the parameter Rz (mean peak-to-valley height). Standard electrodeposited (ED) copper has Rz ~6–10 μm; low-profile (LP) copper ~2–4 μm; very-low-profile (VLP) copper ~1–2 μm; high-VLP (HVLP) copper < 1 μm. At NVLink 5.0 speeds (200 Gb/s per lane, 25 GHz Nyquist), the difference between standard ED and HVLP copper on a 15 cm trace is approximately 2–3 dB of additional insertion loss.
The low-loss laminate market for AI server PCBs is dominated by a small number of suppliers: Panasonic (Megtron series), Isola (Tachyon), and Rogers Corporation (various grades). Shengyi Technology, Taconic, and Park Electrochemical offer additional options. Each supplier's products span a range of Df values and are targeted at different signal speed requirements.
Panasonic's Megtron series is the most widely qualified low-loss laminate family in the AI server PCB industry. Megtron materials are hydrocarbon-based (not traditional epoxy-glass), providing lower Df through inherently lower dielectric polarizability of the resin system.
Megtron 6 (R-5775): The workhorse of the family and the most widely used low-loss laminate in the world. Megtron 6 has Dk ~3.6 and Df ~0.004 at 10 GHz, roughly 5× lower Df than standard FR4. It was the primary material for A100-era GPU boards and remains suitable for NVLink 3.0 and PCIe Gen4 routing layers. For NVLink 4.0 and PCIe Gen5, Megtron 6 is usable on channels up to approximately 150–200 mm with careful design. For NVLink 5.0, Megtron 6 is not recommended on primary signal layers due to insufficient loss budget margin at 200 Gb/s per lane.
Megtron 6E (R-5785): A lower-loss variant of Megtron 6, with Df ~0.0024 at 10 GHz (approximately 40% lower than standard Megtron 6). Megtron 6E is the recommended material for H100-era NVLink 4.0 and PCIe Gen5 signal layers, providing adequate margin for channels up to 200–250 mm. It is also used for PCIe Gen6 on shorter channels (< 150 mm) where Megtron 7 cost is not justified.
Megtron 7 (R-5680): The highest-performance member of the Megtron family commercially available in volume. Dk ~3.4 and Df ~0.002 at 10 GHz. Megtron 7 is the primary material for NVLink 5.0 signal layers on B200 baseboards and NVSwitch 4.0 boards in the GB200 NVL72 rack. It is also used for PCIe Gen6 signal layers on B200 boards. Megtron 7 requires modified press cycles compared to Megtron 6 (different peak temperature and dwell time profiles) and is somewhat more expensive per area, but is readily processable by tier-1 AI server PCB fabricators. As described in the NVIDIA Blackwell Architecture Explained guide, Megtron 7 is essentially the minimum viable material for B200-class board design.
Megtron 8 (development): Panasonic has announced Megtron 8 targeting Df < 0.001 at 10 GHz for next-generation applications beyond NVLink 5.0. Volume availability and fabricator qualification status should be verified before specifying for production programs.
>>>Learn More: Panasonic Megtron 6 vs. Megtron 8: PCB Material Comparison for High-Speed Designs
Isola's Tachyon 100G (I-Tera MT40 is the prepreg companion) is the primary competitor to Panasonic Megtron 6E in the NVLink 4.0 / PCIe Gen5 tier. Dk ~3.6 and Df ~0.0021 at 10 GHz—slightly lower Df than Megtron 6E, making it an excellent choice for H100-era boards and the upper range of PCIe Gen5 channel lengths.
Tachyon 100G is a thermoset resin system that bonds well to standard copper foils and is qualified on the process lines of most tier-1 AI server PCB fabricators. Its processing characteristics are similar to Megtron 6E, making it a drop-in alternative on qualified lines. Some design teams specify Tachyon 100G for NVLink 4.0 layers and Megtron 6 for power and ground planes in the same hybrid stackup, taking advantage of Tachyon's slightly lower Df on the high-speed signal layers while keeping core material cost controlled.
Isola also produces I-Tera MT40 as a standalone laminate system (without the Tachyon 100G designation) with similar properties, and Astra MT77, which targets Df ~0.002 at 10 GHz and is positioned between Tachyon 100G and the Megtron 7 performance tier.
Rogers Corporation is best known for its PTFE-based (polytetrafluoroethylene) microwave laminates, widely used in RF and microwave circuit design. Several Rogers grades are used in AI server PCBs, particularly where the lowest possible Df is required or where coefficient of thermal expansion (CTE) matching to copper or ceramic components is critical.
Rogers RO4350B: A hydrocarbon ceramic laminate (not PTFE) with Dk ~3.48 and Df ~0.0037 at 10 GHz. RO4350B is the most widely used Rogers grade in digital high-speed applications. It has lower Df than standard Megtron 6 but is not in the same tier as Megtron 7 or Tachyon 100G. Its processing characteristics are more similar to conventional epoxy laminates than to PTFE, making it processable on standard FR4 press lines with appropriate parameter adjustment. RO4350B is used in some AI server applications for PCIe Gen5 signal layers where its intermediate Df is adequate, and for high-frequency RF sections of boards that require better Df than FR4 without moving to premium Megtron-class materials.
Rogers RO4450F: A bonding prepreg designed to be used with RO4350B or other Rogers laminates in multilayer constructions. Its Df ~0.0037 at 10 GHz matches RO4350B, providing consistent dielectric properties through the stackup when Rogers materials are used on multiple layers.
Rogers RO3003 and RO3010: PTFE-based laminates with very low Df (< 0.001 at 10 GHz) intended for microwave and millimeter-wave applications. These materials have processing challenges in multilayer digital PCBs—PTFE does not bond as reliably to standard oxide-treated inner layers and requires plasma etch or chemical adhesion promotion treatments before lamination. They are generally not used as the primary structural laminate in AI server baseboards, but may appear in hybrid constructions where a specific layer requires the absolute lowest possible dielectric loss (for example, a 224G PAM4 routing layer discussed in articles covering next-generation AI data center interconnects).
Rogers 4830: A woven-glass-reinforced PTFE laminate with Dk ~3.0 and Df ~0.0014 at 10 GHz, offering performance between standard hydrocarbon laminates and pure PTFE. Occasionally specified for NVLink 5.0 or 224G PAM4 applications where Megtron 7 does not provide sufficient margin and the processing challenges of pure PTFE are unacceptable.
Shengyi S1000-2M / S7439: Shengyi Technology is a major Chinese laminate supplier that has developed Megtron-equivalent materials targeting the same Df performance tier. Shengyi S7439 targets Df ~0.003–0.004 at 10 GHz and is used by some Asian ODMs and PCB fabricators as a cost-effective alternative to Panasonic Megtron 6 on A100 and H100-era boards. Qualification status with specific fabricators should be verified before specifying.
Taconic TLY and TLX series: PTFE-woven-glass laminates from Taconic targeting Df < 0.002 at 10 GHz. Processability in multilayer AI server board constructions has the same challenges as Rogers PTFE grades. Primarily used in RF subsystems within mixed-signal boards rather than as the primary AI server signal laminate.
Ventec VT-901: A halogen-free low-loss laminate targeting Df ~0.005 at 1 GHz, positioned for PCIe Gen4 and lower-speed applications where halogen-free certification is required. Not suitable as the primary material for NVLink 4.0 or Gen5/Gen6 signal layers.
Copper foil selection is as important as laminate selection for AI server PCB performance, because conductor loss at NVLink and PCIe Gen5/6 frequencies is comparable in magnitude to dielectric loss on a well-optimized channel.
| Foil Grade | Rz (Surface Roughness) | Approximate Conductor Loss vs ED at 16 GHz | Typical Application |
|---|---|---|---|
| Standard ED (Electrodeposited) | 6–10 μm | Baseline (reference) | Standard FR4 boards; not suitable for AI server signal layers |
| Low-Profile (LP) | 2–4 μm | −0.5–1.0 dB on 15 cm trace | PCIe Gen4; minimum for PCIe Gen5 short channels |
| Very-Low-Profile (VLP) | 1–2 μm | −1.0–2.0 dB on 15 cm trace | NVLink 4.0; PCIe Gen5; PCIe Gen6 short channels |
| High-VLP (HVLP) | < 1 μm | −1.5–3.0 dB on 15 cm trace | NVLink 5.0; PCIe Gen6; 112G PAM4; 224G PAM4 |
Copper foil roughness also affects laminate bonding: rougher foil provides more mechanical interlocking surface area for the resin and typically bonds more strongly. HVLP copper has less mechanical adhesion to the resin and requires careful laminate-foil combination qualification. Not all low-loss laminates are qualified with HVLP foil by the laminate manufacturer; this compatibility must be verified before specifying an HVLP/Megtron 7 combination for production. Panasonic qualifies Megtron 7 with HVLP foil options and provides peel strength data; Isola similarly qualifies Tachyon 100G with multiple foil grades.
One additional effect of foil roughness is its contribution to Dk uncertainty. The foil-dielectric interface roughness creates a fringe capacitance effect that shifts the effective Dk upward slightly; smoother foils have less of this effect, and moving from ED to HVLP copper on the same laminate can reduce the effective Dk by approximately 0.05–0.15, which slightly affects the impedance of the finished board and must be accounted for in the stackup design.
| Material | Supplier | Dk (10 GHz) | Df (10 GHz) | Tg (°C) | Recommended Foil | AI Server Use Case |
|---|---|---|---|---|---|---|
| Standard FR4 | Multiple | ~4.5 | ~0.020 | 130–170 | ED | Not suitable for AI server signal layers |
| Megtron 6 (R-5775) | Panasonic | ~3.6 | ~0.004 | 185 | LP / VLP | A100-era NVLink 3.0; power/ground planes on all AI boards |
| Megtron 6E (R-5785) | Panasonic | ~3.4 | ~0.0024 | 185 | VLP | H100 NVLink 4.0; PCIe Gen5; PCIe Gen6 short channels |
| Megtron 7 (R-5680) | Panasonic | ~3.4 | ~0.002 | 185 | HVLP | B200 NVLink 5.0; PCIe Gen6; NVSwitch 4.0 boards; 112G PAM4 |
| Tachyon 100G | Isola | ~3.6 | ~0.0021 | ~185 | VLP | H100 NVLink 4.0; PCIe Gen5; alternative to Megtron 6E |
| Astra MT77 | Isola | ~3.4 | ~0.002 | ~185 | VLP / HVLP | NVLink 5.0; PCIe Gen6; B200-class boards |
| I-Tera MT40 | Isola | ~3.45 | ~0.0028 | ~185 | VLP | NVLink 4.0; PCIe Gen5; prepreg companion to Tachyon |
| RO4350B | Rogers | ~3.48 | ~0.0037 | 280+ | VLP | PCIe Gen5 moderate channels; RF subsections |
| RO4450F (prepreg) | Rogers | ~3.52 | ~0.0037 | 280+ | N/A (prepreg) | Bonding layer for RO4350B multilayer constructions |
| RO3003 | Rogers | ~3.0 | ~0.001 | >500 (PTFE) | VLP / ED | Specialized: 224G PAM4; millimeter-wave applications; challenging to process in multilayer |
| Shengyi S7439 | Shengyi | ~3.6 | ~0.003–0.004 | ~185 | LP / VLP | A100/H100-tier alternative; verify fabricator qualification |
Note: All Dk and Df values are approximate and frequency-dependent. Always use fabricator-measured values and the specific laminate product datasheet for design calculations. Df typically increases with frequency; verify values at the actual operating frequency for the signal type being routed.
The correct laminate selection depends on which signals the layer must carry. AI server baseboards route multiple signal types simultaneously, and the material requirement is driven by the highest-speed signal on each layer. The following table summarizes the recommended material tier for each major AI server signal interface, drawing on the detailed analysis in the AI Accelerator PCB Design Guide and the NVLink-specific guidance in What Is NVLink?
| Signal Interface | Speed | Nyquist / Fundamental | Minimum Laminate Df | Recommended Laminate | Copper Foil |
|---|---|---|---|---|---|
| PCIe Gen4 | 16 GT/s per lane | 8 GHz | ≤ 0.006 | Megtron 6 | LP |
| PCIe Gen5 | 32 GT/s per lane | 16 GHz | ≤ 0.003 | Megtron 6E / Tachyon 100G | VLP |
| PCIe Gen6 (PAM4) | 64 GT/s per lane | 16 GHz (PAM4) | ≤ 0.002 | Megtron 7 / Astra MT77 | HVLP |
| NVLink 3.0 (A100) | ~50 Gb/s per lane | ~12.5 GHz | ≤ 0.005 | Megtron 6 | LP |
| NVLink 4.0 (H100) | 100 Gb/s per lane | ~25 GHz | ≤ 0.003 | Megtron 6E / Tachyon 100G | VLP |
| NVLink 5.0 (B200) | 200 Gb/s per lane | ~25–50 GHz | ≤ 0.002 | Megtron 7 / Astra MT77 | HVLP |
| 112G PAM4 (Ethernet / InfiniBand) | 112 Gb/s per lane | ~14 GHz (PAM4) | ≤ 0.002 | Megtron 7 / Tachyon 100G | VLP / HVLP |
| 224G PAM4 | 224 Gb/s per lane | ~28 GHz (PAM4) | ≤ 0.001 | Megtron 7 or PTFE-based (RO3003) | HVLP |
| Power and ground planes | DC / low frequency | N/A | No constraint | Megtron 6 or FR4-class | 2–3 oz ED or LP |
| Management / low-speed signals | < 1 Gb/s | < 0.5 GHz | No constraint | Megtron 6 or FR4-class | 1 oz ED or LP |
The 112G PAM4 PCB Design guide provides detailed trace routing and SI rules for 112G channels on Megtron 7 and equivalent ultra-low-loss materials, which are increasingly standard in AI server NIC and switching subsections.
A fully homogeneous stackup—the same material on every layer—is rarely optimal for an AI server baseboard. The highest-performance (and highest-cost) laminates are needed only on the layers carrying the fastest signals. Power and ground planes, management signal layers, and HDI build-up layers do not benefit from Megtron 7 and can use lower-cost materials without any performance penalty.
A hybrid stackup mixes low-loss laminate on the critical signal layers with standard Megtron 6 or equivalent on non-critical layers, achieving the necessary signal integrity performance at a materially lower board cost. A representative hybrid stackup for a 28-layer B200-class baseboard might allocate Megtron 7 to 8 NVLink 5.0 signal routing layers and 1 PCIe Gen6 layer, Megtron 6 to 10 power/ground plane layers and 2 management signal layers, and build-up prepreg (compatible with Megtron 7) to the 4 HDI layers. Megtron 7 represents perhaps 32% of the total layer count but addresses 100% of the signal integrity requirement, while Megtron 6 on the remaining layers keeps the overall board material cost significantly below a full-Megtron-7 design.
Hybrid stackup design requires careful attention to two compatibility issues. First, the bonding chemistry between adjacent layers of different material types must be compatible; Megtron 6 and Megtron 7 bond well to each other and to standard prepregs, but mixing PTFE-based Rogers materials with hydrocarbon laminates requires surface treatment steps that complicate processing. Second, the coefficient of thermal expansion (CTE) of adjacent materials should be similar to prevent interlaminar stress during thermal cycling; Megtron 6 and Megtron 7 have nearly identical CTE, making them ideal hybrid partners.
Fabricators who have established hybrid stackup processes for AI server boards maintain approved material combinations and bonding protocols. Specifying a novel material combination without verifying fabricator qualification is a common source of delamination failures in prototype programs. The manufacturing implications of hybrid stackup design are discussed in detail in How GPU PCBs Are Manufactured: From Bare Board to Final PCBA.
Low-loss laminates require process adaptations compared to standard FR4 production. Engineers specifying these materials for AI server boards should be aware of the following manufacturing considerations when working with fabricators.
Storage and handling: Low-loss laminates are more sensitive to moisture and temperature than standard FR4. Megtron 6/7 and Tachyon 100G should be stored in sealed packaging in temperature-controlled (20–25°C) and humidity-controlled (< 40% RH) environments. Moisture absorption before lamination can cause blistering during press cycles and degrades the cured dielectric's Df. Pre-baking of panels before lamination is standard practice for high-reliability AI server board production.
Press cycle qualification: The resin system in Megtron 7 has different cure kinetics than standard FR4 or even Megtron 6. Optimal press temperature, ramp rate, dwell time, and pressure must be established and qualified for each material system. Megtron 7 typically requires a slightly higher peak temperature and longer dwell compared to Megtron 6 to achieve full cure (Tg ≥ 185°C). Under-cured Megtron 7 has degraded Df and reduced reliability under thermal cycling.
Drilling: Low-loss laminates with woven glass reinforcement (Megtron 6/7, Tachyon 100G) drill similarly to standard FR4. PTFE-based laminates (Rogers RO3003) are soft and deform under drill pressure, requiring specialized drill bits and entry/backup materials. Laser drilling of microvias in Megtron 7 prepreg requires CO2 laser parameters qualified for that material's dielectric absorption characteristics; Megtron 7 prepreg absorbs CO2 laser energy somewhat differently than standard prepreg and may require adjusted pulse energy or repetition rate.
Copper foil compatibility: HVLP copper foil bonds less strongly to laminate resin than standard ED copper, requiring that the foil-laminate combination be qualified for minimum peel strength per IPC-4101. Panasonic qualifies Megtron 7 with specific HVLP foil grades and provides peel strength specifications; substituting unqualified foil grades risks delamination under the thermal cycling of AI server operation.
Impedance control: Low-loss laminates generally have tighter and more predictable Dk than standard FR4, which benefits impedance control. However, the lower Dk of Megtron 7 (~3.4) compared to FR4 (~4.5) means that for the same differential impedance target (85 Ω for PCIe / NVLink), trace widths must be adjusted compared to FR4-based stackup calculations. Fabricators must use measured Dk values for the specific material lot in their impedance calculation, not nominal datasheet values, and must provide TDR coupon data from the same production run to verify ± 5% impedance tolerance.
Cost premium: Megtron 7 and Tachyon 100G carry a significant cost premium over standard FR4. As a rough order of magnitude, Megtron 7 cores and prepregs cost approximately 3–5× the price of equivalent FR4 materials per unit area. For an AI server baseboard where 30–40% of layers use Megtron 7, the material cost premium over an all-FR4 board is approximately 1.5–2.5×. This cost must be weighed against the cost of signal integrity failures, retimer components needed to compensate for inferior material performance, and the program risk of board respins due to channel compliance failures on cheaper material.
What is the most commonly used PCB material for H100 GPU server boards?
H100-era GPU baseboard designs most commonly use Panasonic Megtron 6E or Isola Tachyon 100G on NVLink 4.0 signal routing layers, with Panasonic Megtron 6 on power and ground plane layers. This hybrid stackup provides the necessary signal integrity performance for NVLink 4.0 at 100 Gb/s per lane while keeping overall board material cost below a full-premium-material design. The A100-to-H100 transition and its material implications are analyzed in A100 vs H100: GPU Generational Leap & PCB Stack Differences Explained.
Can Megtron 6 be used for NVLink 5.0?
Not on the primary NVLink 5.0 signal routing layers. At 200 Gb/s per lane (NVLink 5.0) with a Nyquist-adjacent frequency content extending to 25–50 GHz, Megtron 6's Df of ~0.004 generates insufficient channel margin at the trace lengths (10–20 cm) typical of GPU-to-NVSwitch routing on an AI server baseboard. Megtron 7 (Df ~0.002) is the minimum viable laminate for NVLink 5.0 signal layers. Megtron 6 remains appropriate for power and ground plane layers in the same board, which is why hybrid Megtron 7 / Megtron 6 stackups are the standard for B200-class board designs.
Is Rogers RO4350B a good choice for AI server PCBs?
RO4350B is a competent material for PCIe Gen5 channels of moderate length (< 150 mm) and for RF subsections of mixed-signal AI server boards. Its Df of ~0.0037 at 10 GHz is better than Megtron 6 but worse than Megtron 6E or Tachyon 100G, placing it in an intermediate performance tier. Its Tg > 280°C is an advantage for high-temperature applications. For the primary NVLink 4.0 signal layers, Megtron 6E or Tachyon 100G are generally preferred because their Df is lower and their processing is more straightforward in multilayer sequential lamination. RO4350B is more commonly used in dedicated RF board sections than as the primary AI server signal laminate.
Why does HVLP copper cost more and is it always necessary?
HVLP copper (Rz < 1 μm) is manufactured by an electrodeposition process that deposits copper more slowly and with tighter process control than standard ED copper, increasing production cost by approximately 20–40% over LP copper. It is necessary on AI server signal layers when the conductor loss contribution from standard or LP foil would consume enough of the channel insertion loss budget to cause compliance failures or insufficient margin. For NVLink 5.0 at 200 Gb/s per lane, the 1.5–3.0 dB saved by HVLP vs standard ED copper on a 15 cm trace is the difference between a compliant and non-compliant channel in many designs. For PCIe Gen4 or NVLink 3.0 layers, LP copper is adequate and HVLP is unnecessary cost.
How does moisture affect low-loss laminate performance?
Moisture absorption increases the effective Dk and Df of dielectric materials. Standard FR4 absorbs 0.1–0.4% water by weight in humid environments; Megtron 6/7 is designed for low moisture absorption (< 0.1% typically). Even small amounts of moisture increase Df because water has a high Df itself (~0.05 at 10 GHz) and the absorbed water molecules polarize in the applied electric field, adding to the material's dielectric loss. Pre-baking boards and panels before press cycles removes absorbed moisture and ensures that the laminate's specified Df is achieved in the finished board. AI server boards operating in high-humidity data center environments should be conformally coated if the PCB has moisture-sensitive signal paths, though this is rarely required in practice.
Which material should I specify for a board that mixes PCIe Gen5 and NVLink 4.0 in the same stackup?
Both PCIe Gen5 and NVLink 4.0 operate with comparable frequency content (16 GHz Nyquist for Gen5; ~25 GHz fundamental for NVLink 4.0) and have similar material requirements. Megtron 6E or Tachyon 100G (Df ~0.002–0.003 at 10 GHz) with VLP copper is the recommended material for layers carrying either of these signal types. Since the NVLink 4.0 requirement is slightly more demanding than Gen5, specifying Megtron 6E (rather than standard Megtron 6) ensures that both interfaces are adequately served by the same material on the same signal layers—simplifying the stackup and the fabrication process simultaneously. This approach is standard practice on H100 HGX baseboards, as detailed in Why AI GPUs Require 30+ Layer HDI PCBs.
NextPCB processes the full range of low-loss AI server laminates—Panasonic Megtron 6, Megtron 6E, Megtron 7, Isola Tachyon 100G, Rogers RO4350B, and hybrid stackup combinations—with qualified press cycles, HVLP copper foil capability, ± 5% impedance control, and IPC Class 3 quality standards for AI server PCB programs from prototype through production.
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