How Many Vias Under QFN Thermal Pad? Count & Size Guide

When placing an STM32 or any other QFN-packaged IC on a PCB, the number of thermal vias under the exposed center pad is one of the most consequential DFM decisions in the entire layout. Too few vias and the thermal resistance from die to PCB is too high, causing junction temperature rise under sustained load. Too many vias with incorrect diameters and solder siphoning during reflow creates voids that defeat the thermal pad's purpose entirely.

This article gives you the specific via count, diameter, pitch, and array geometry recommendations for QFN thermal pads across common STM32 package sizes, along with the DFM constraints that govern each parameter. For context on why the thermal pad must be grounded and what happens when it is not, refer to Should STM32 Thermal Pad Be Grounded? For the complete STM32 layout checklist covering impedance routing and HDI design rules, see the STM32 Pinout and Package Guide.

1. Table of Contents
2. 1. Why Via Count Under a QFN Thermal Pad Matters
3. 2. Quick Answer: How Many Vias for Common STM32 QFN Packages
4. 3. Via Diameter: The Parameter That Constrains Everything Else
5. 4. Via Pitch and Spacing Rules
6. 5. How Via Count Affects Thermal Resistance: The Numbers
7. 6. Solder Siphoning: The Risk That Limits Via Diameter
8. 7. VIPPO vs. Tenting: When Each Is Required
9. 8. Applying These Rules to Non-STM32 QFN Packages
10. 9. QFN Thermal Via DFM Checklist
11. 10. Frequently Asked Questions

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1. Why Via Count Under a QFN Thermal Pad Matters

The exposed thermal pad on a QFN package has two simultaneous functions: it is the primary heat extraction path from the die to the PCB, and it is the lowest-impedance ground return for all switching currents inside the MCU. Both functions are served by the same physical connection — the solder joint between the pad and the PCB copper — and both are degraded in proportion to the quality of that connection.

Via count directly determines three measurable outcomes:

• Thermal resistance (θ_JB): Each via in direct copper contact with an internal ground plane provides a parallel thermal conduction path. Adding vias reduces the total thermal resistance from the pad to the plane, lowering the die junction temperature at a given power dissipation level.
• Ground impedance at high frequency: At 80–160 MHz switching frequencies (typical STM32 operating ranges), the inductance of the ground return path is a meaningful noise source. More vias in parallel reduce the effective inductance of the thermal pad-to-plane connection, lowering the high-frequency ground impedance and reducing substrate-coupled noise on sensitive analog rails.
• Solder void risk: More vias mean more potential siphoning sites during reflow. This creates a direct trade-off: more vias improve thermal and electrical performance but increase the probability of solder being drawn away from the pad surface into the via barrels, creating voids that reduce the effective contact area and partially negate the benefit of additional vias.

The goal is not to maximize via count — it is to find the count and geometry that achieves sufficient thermal conductance and ground impedance while keeping solder void area below the acceptance threshold for your application class.

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2. Quick Answer: How Many Vias for Common STM32 QFN Packages

For engineers who need the number immediately:

STM32 Package	Thermal Pad Size	Recommended Array	Via Count	Via Finished Hole Diameter	Via Pitch
UFQFPN20 (3 × 3 mm body)	1.7 × 1.7 mm	2 × 2	4 vias	0.2–0.25 mm	0.6 mm
UFQFPN28 (4 × 4 mm body)	2.5 × 2.5 mm	2 × 2 to 3 × 3	4–9 vias	0.2–0.3 mm	0.7 mm
UFQFPN32 (5 × 5 mm body)	3.4 × 3.4 mm	3 × 3	9 vias	0.2–0.3 mm	0.8 mm
UFQFPN48 (7 × 7 mm body)	5.4 × 5.4 mm	4 × 4	16 vias	0.2–0.3 mm	1.0 mm
UFQFPN48 (7 × 7 mm), high-reliability	5.4 × 5.4 mm	5 × 5	25 vias	0.2–0.25 mm (VIPPO required)	0.8 mm

These counts assume via diameters within the 0.2–0.3 mm finished hole range, direct copper connection to the ground plane (no thermal relief), and standard FR4 PCB material. The rationale for each parameter is explained in the sections below. If your design uses VIPPO processing, via diameters can be increased to 0.3–0.4 mm without siphoning risk, allowing a smaller array count to achieve equivalent thermal performance.

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3. Via Diameter: The Parameter That Constrains Everything Else

Via diameter is the single most important parameter in thermal via design because it controls solder siphoning risk, fabrication cost, and the thermal conductance per via simultaneously. The three variables are in direct tension with each other:

Finished Hole Diameter	Siphoning Risk	Thermal Conductance per Via	Fabrication Cost Impact	Verdict
< 0.15 mm	Negligible	Poor — insufficient copper barrel cross-section	High — requires laser drill or tight mechanical tolerance	Not recommended
0.15–0.2 mm	Very low	Moderate	Moderate — at limit of standard mechanical drill	Acceptable for very small pads only
0.2–0.3 mm	Low to moderate	Good	Standard — no premium process required	Preferred range for all standard QFN thermal pads
0.3–0.4 mm	High without VIPPO	Very good	Standard drill; VIPPO adds cost	Acceptable only with VIPPO fill and copper cap
> 0.4 mm	Very high — all solder wicks into barrel	Excellent per via	Standard	Not recommended under SMT pads under any circumstance

3.1 Why 0.2–0.3 mm Is the Standard Range

The solder siphoning threshold is governed by capillary action physics. The capillary pressure driving solder into a via barrel is inversely proportional to the via radius — smaller vias generate higher capillary pressure, which counterintuitively means small vias actually draw solder in more aggressively than large ones at very small diameters. However, below approximately 0.2 mm diameter, the capillary action reverses and becomes self-limiting because the surface tension of the solder meniscus exceeds the gravitational and reflow-pressure forces trying to push solder into the barrel.

Above approximately 0.3 mm, the via barrel volume is large enough that even with partial siphoning, the solder loss from the pad surface is significant. At 0.4 mm and above, a single via can consume enough solder paste to leave the surrounding pad area insufficiently wetted, creating the circular void pattern visible on X-ray around each large via opening.

The 0.2–0.3 mm range sits in the practical optimum: fabricatable with standard mechanical drills at no cost premium, low enough capillary pressure to minimize siphoning without tenting or fill, and large enough barrel cross-section to provide meaningful thermal conductance per via.

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4. Via Pitch and Spacing Rules

Via pitch within the thermal pad must satisfy two constraints simultaneously: it must be large enough to meet the PCB fabricator's minimum annular ring and drill-to-drill spacing rules, and it must be small enough to distribute thermal vias evenly across the pad without creating large un-viaed copper islands that act as thermal dead zones.

Parameter	Minimum	Maximum	Recommended
Via center-to-center pitch	0.5 mm (constrained by annular ring + drill spacing)	1.2 mm (beyond this, thermal dead zones form between vias)	0.6–1.0 mm depending on pad size
Via edge to pad edge clearance	0.15 mm minimum	—	0.2–0.25 mm to ensure solder mask dam integrity
Via edge to solder mask opening edge	0.1 mm inside the mask opening	—	Center vias well within the copper pad area
Drill-to-drill clearance (edge to edge)	0.2 mm (standard fab capability)	—	0.3 mm for reliable drill registration

4.1 Array Symmetry Requirement

Via arrays under thermal pads must be geometrically symmetric (square arrays: 2×2, 3×3, 4×4, 5×5) rather than irregular or row-based patterns. Symmetric arrays ensure uniform solder paste distribution during stencil printing — an asymmetric via pattern creates differential capillary forces during reflow that can cause the package to rotate slightly as the solder wets unevenly, pulling fine-pitch perimeter leads off their pads.

4.2 Minimum Edge Distance from Pad Boundary

Vias must not be placed at the very edge of the thermal pad copper area. A minimum clearance of 0.15–0.2 mm between the via barrel edge and the pad copper boundary is required to prevent the drill from breaking through the pad edge during fabrication, which creates a copper burr that affects solder paste printing across the stencil aperture.

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5. How Via Count Affects Thermal Resistance: The Numbers

Each plated through-hole via connecting the thermal pad to an internal copper plane provides a discrete thermal conduction path. The total thermal resistance of the via array in parallel can be approximated as:

θ_{via_total} = θ_{via_single} ÷ N

where N is the number of vias and θ_{via_single} is the thermal resistance of a single via. For a 0.25 mm finished hole via with 1 oz copper plating in a standard 1.6 mm FR4 board, θ_{via_single} is approximately 70–90°C/W. This gives the following thermal resistance contributions by array size:

Array	Via Count (N)	θvia_total (approx., °C/W)	Improvement vs. Previous
2 × 2	4	~18–22	Baseline for small pads
3 × 3	9	~8–10	~55% reduction vs. 2×2
4 × 4	16	~4.5–5.5	~45% reduction vs. 3×3
5 × 5	25	~3.0–3.5	~35% reduction vs. 4×4
6 × 6	36	~2.0–2.5	~28% reduction vs. 5×5

The diminishing returns are clear: going from 4 to 9 vias halves the thermal resistance, but going from 16 to 25 vias achieves only a 35% reduction while adding 9 additional siphoning sites. For most STM32 applications where MCU power dissipation is below 500 mW, a 3×3 or 4×4 array is sufficient to keep junction temperature well within the 85°C or 125°C rated maximum. A 5×5 array is warranted only for sustained high-current applications or when the ambient temperature is elevated (industrial environments above 70°C ambient).

The via array thermal resistance must be added in series with the pad-to-copper thermal resistance (typically 0.5–2°C/W for a well-soldered joint) and the board spreading resistance (depends on copper pour area and layer count) to calculate total θ_JB. Always verify against the package datasheet's rated θ_JB value — if your calculated via array resistance significantly exceeds the datasheet θ_JB, the via array is the bottleneck and adding vias will help. If your calculated value is already below the datasheet figure, additional vias provide no meaningful benefit.

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6. Solder Siphoning: The Risk That Limits Via Diameter

Solder siphoning (also called solder wicking) is the process by which molten solder paste flows from the pad surface into via barrels during reflow, driven by capillary action. It is the primary DFM risk associated with thermal vias under QFN pads and the reason via diameter must be controlled within the 0.2–0.3 mm range.

6.1 The Mechanism

During reflow, solder paste melts at approximately 183°C (Sn63Pb37) or 217°C (SAC305 lead-free). In the liquid state, the surface tension of the solder interacts with the copper-plated via barrel walls. If the via barrel is large enough that the solder meniscus can form a stable contact angle with the copper walls, the liquid solder will flow downward under gravity and capillary forces — away from the pad surface and into the barrel.

The consequences of siphoning are:

• The solder volume available to wet the thermal pad surface decreases, creating dry areas (voids) in the finished joint.
• The solder that wicked into the via barrel may solidify partially inside the barrel rather than on either copper pad surface, creating a barrel-fill joint with reduced mechanical strength.
• In severe cases, solder from the thermal pad migrates through the via to the opposite board surface, potentially bridging the thermal via exit pad to an adjacent trace on the back copper layer.

6.2 Quantifying the Siphoning Risk by Via Diameter

Via Diameter	Barrel Volume (1.6 mm board, approx.)	Solder Volume per Via Siphoned (worst case)	Risk Level
0.2 mm	~0.05 mm³	~0.03–0.04 mm³	Low — siphoned volume is small relative to stencil deposit
0.25 mm	~0.08 mm³	~0.05–0.06 mm³	Low to moderate
0.3 mm	~0.11 mm³	~0.08–0.10 mm³	Moderate — aggregate across 16 vias becomes significant
0.4 mm	~0.20 mm³	~0.15–0.18 mm³	High — equivalent to removing one full stencil aperture segment
0.5 mm	~0.31 mm³	~0.25–0.30 mm³	Very high — will cause visible voids and possible component float

6.3 Mitigation Strategies in Priority Order

• Keep via diameter ≤ 0.3 mm (primary control): The most effective mitigation. At 0.3 mm and below, the aggregate siphoned volume from a 4×4 array is typically below the void acceptance threshold for IPC Class 2.
• VIPPO processing (eliminates siphoning entirely): Epoxy-filled, copper-capped vias present a flat copper surface to the solder paste. No barrel is available for solder to wick into. Allows larger via diameters if needed for thermal reasons.
• Solder mask tenting on top surface: Dry-film solder mask over the via opening on the top surface blocks the solder meniscus from forming. Less reliable than VIPPO on small diameters but eliminates the process cost premium.
• Stencil aperture segmentation: Designing the stencil aperture as a grid rather than a solid block ensures solder paste is deposited around via openings rather than directly over them, reducing the direct siphoning path. This does not eliminate siphoning but reduces it meaningfully in combination with small via diameters.

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7. VIPPO vs. Tenting: When Each Is Required

Scenario	VIPPO	Tenting	Neither (bare via)
Via diameter ≤ 0.25 mm, standard application	Optional — improves yield	Acceptable	Acceptable with segmented stencil
Via diameter 0.25–0.3 mm, standard application	Recommended	Acceptable	Marginal — monitor void % with X-ray
Via diameter > 0.3 mm	Required	Not sufficient	Not acceptable
IPC Class 3 (automotive, medical)	Required regardless of diameter	Not acceptable for Class 3	Not acceptable
High-volume production (> 1000 units)	Strongly recommended	Acceptable if X-ray sampling shows < 25% voids	Risk of yield variation across production lots
Prototype / low-volume (< 50 units)	Optional	Acceptable	Acceptable with 0.2–0.25 mm vias and segmented stencil

7.1 How to Specify VIPPO in Your Fabrication Notes

VIPPO must be explicitly called out — it is not assumed by fabricators as a default process. When submitting Gerber files for PCB prototype fabrication, include the following in your fabrication drawing notes:

• "Via-in-pad plated over (VIPPO) required on all vias located within the thermal pad copper area of [reference designator]. Fill with non-conductive epoxy, copper plate, and planarize flush with pad surface. Finished surface height deviation ≤ 10 µm."
• Identify the thermal pad vias explicitly in a separate via table or by layer annotation in the fabrication drawing.
• Include a cross-section note if IPC Class 3 is required: "Cross-section microsection required on 1 coupon per panel to verify epoxy fill integrity and copper cap thickness ≥ 5 µm."

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8. Applying These Rules to Non-STM32 QFN Packages

The via count and geometry rules described in this article apply to any QFN package with an exposed thermal pad, regardless of manufacturer. The key input variable is the thermal pad size, not the package body size or pin count. Use the following formula to determine the appropriate array for any QFN pad:

Array dimension N = floor((Pad_dimension − 2 × Edge_clearance) ÷ Via_pitch) + 1

For a pad of 4.0 mm × 4.0 mm with 0.2 mm edge clearance and 0.9 mm pitch:

N = floor((4.0 − 0.4) ÷ 0.9) + 1 = floor(3.6 ÷ 0.9) + 1 = floor(4) + 1 = 5

This gives a 5×5 = 25-via array — appropriate for a 4.0 mm thermal pad. For a tighter pitch of 1.0 mm on the same pad: N = floor(3.6 ÷ 1.0) + 1 = 4, giving a 4×4 = 16-via array. Both are valid; the choice depends on whether your fabricator supports 0.9 mm pitch reliably at the drill diameter you have specified.

Thermal Pad Size	Recommended Array	Via Count	Applicable QFN Examples
1.5 × 1.5 mm or smaller	2 × 2	4	QFN16 (3×3 mm body), very small MCUs
1.5–2.5 mm	2 × 2 to 3 × 3	4–9	QFN20, QFN24 small body variants
2.5–3.5 mm	3 × 3	9	STM32 UFQFPN32, typical QFN32
3.5–5.0 mm	3 × 3 to 4 × 4	9–16	QFN44, QFN48 medium body
5.0–6.0 mm	4 × 4 to 5 × 5	16–25	STM32 UFQFPN48, power management ICs
> 6.0 mm	5 × 5 or custom	25+	Large QFN power devices, RF transceivers

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9. QFN Thermal Via DFM Checklist

DFM Item	Requirement	Verified?
Via finished hole diameter	0.2–0.3 mm for standard process; 0.3–0.4 mm only with VIPPO	☐
Via array geometry	Square symmetric array (2×2, 3×3, 4×4, or 5×5) — no irregular patterns	☐
Via count vs. pad size	≥ 9 vias (3×3) for pads ≥ 3.4 mm; ≥ 16 vias (4×4) for pads ≥ 5.0 mm	☐
Via center-to-center pitch	0.6–1.0 mm; minimum 0.5 mm	☐
Via edge to pad boundary clearance	≥ 0.15 mm; recommended 0.2 mm	☐
Drill-to-drill spacing (edge to edge)	≥ 0.2 mm; recommended 0.3 mm	☐
Ground plane connection	Direct solid copper fill to VSS plane — no thermal relief spokes	☐
Stencil aperture	Segmented grid; 50–75% total coverage; channels ≥ 0.2 mm between segments	☐
Stencil aperture alignment to vias	Aperture segment centers offset from via centers — no direct alignment	☐
Via treatment	VIPPO specified if diameter > 0.3 mm or IPC Class 3 required; tenting acceptable otherwise	☐
VIPPO fab note	Explicit VIPPO callout in fabrication drawing notes if required	☐
Back-side copper clearance	No signal traces within 0.2 mm of thermal via exit pads on bottom copper layer	☐
Post-assembly X-ray inspection	Void area target < 25% (IPC Class 2) or < 10% (IPC Class 3) of thermal pad area	☐
Continuity check	DC resistance from thermal pad via to VSS test point < 1 Ω	☐

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Related NextPCB Services

• PCB Prototype with VIPPO — Via-in-pad epoxy fill and copper cap planarization specified per fabrication note. Anchor text: "PCB prototype with VIPPO" → nextpcb.com/pcb-prototype
• PCB Assembly with X-Ray Void Inspection — QFN thermal pad void analysis with percentage reporting before shipment. Anchor text: "PCB assembly service" → nextpcb.com/pcb-assembly
• HDI PCB Manufacturing — Supports blind/buried via fanout adjacent to thermal pad areas in HDI stackups. Anchor text: "HDI PCB manufacturing" → nextpcb.com/hdi-pcb

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Frequently Asked Questions

Q1: Is there a maximum number of vias I should not exceed under a QFN thermal pad?

There is no hard maximum, but there is a practical optimum beyond which additional vias create more siphoning risk than thermal benefit. For a 5.4 mm × 5.4 mm pad (STM32 UFQFPN48), a 5×5 array of 25 vias is typically the upper practical limit at 0.25 mm diameter and 0.8 mm pitch. Beyond 25 vias on a pad this size, the pitch must decrease below 0.8 mm to fit within the pad boundary — at which point drill-to-drill spacing constraints at most fabricators become the binding limitation, not thermal requirements.

Q2: Can I use a single large via instead of an array of small vias?

No. A single large via (e.g., 0.8 mm or 1.0 mm) under a QFN thermal pad will cause severe solder siphoning — the entire solder paste deposit for that area of the pad will wick into the barrel during reflow. Beyond the siphoning problem, a single via provides only one thermal conduction path and no redundancy against void formation. Array designs are mandatory for QFN thermal pads.

Q3: Do thermal vias under the pad need to connect to every ground plane in the stackup?

They should connect to as many ground copper layers as your stackup allows, but the most important connection is to the first internal ground plane (Layer 2 in a standard 4-layer stackup). This layer is closest to the thermal pad and provides the highest-area copper pour for heat spreading. Connecting to additional ground planes (Layer 3 or beyond) provides incremental improvement in thermal spreading resistance but is not required for adequate thermal performance in most STM32 applications.

Q4: My PCB has only 2 layers. How should I handle the thermal via under a QFN pad?

On a 2-layer board, thermal vias connect the top copper pour under the QFN pad directly to the bottom copper ground pour. Heat spreading occurs on both the top and bottom copper layers. The thermal resistance is higher than a 4-layer board because there are no internal copper planes for heat spreading, but the via array itself functions identically. Maximize the bottom copper pour area connected to the via exits to compensate for the reduced spreading area. On a 2-layer board, VIPPO is particularly important because the via exits on the bottom copper are easily accessible to solder from the paste printing process and siphoning risk is higher.

Q5: How do I verify the via count in my PCB layout tool matches what was fabricated?

Request a drill report from your fabrication partner that lists finished hole sizes and counts per drill layer. Cross-reference this against your design's drill file. For VIPPO vias specifically, request a cross-section microsection on a test coupon from the production panel — this is the only definitive verification method for epoxy fill integrity and copper cap thickness.

Q6: Does the via array under the thermal pad need a solder mask opening on the bottom side?

The bottom-side via exit pads should have solder mask over them (NSMD tenting) if you are not using VIPPO and do not want solder paste applied to the bottom of the board during top-side assembly. If the board undergoes double-sided reflow (SMT components on both sides), the bottom via exit pads must be tented with solder mask to prevent paste from being applied there during bottom-side stencil printing. If the board is single-sided assembly, bottom tenting is optional but recommended to prevent solder from wicking onto the via exit copper during top-side reflow.