Common HDI Stackup Types (1+N+1, 2+N+2 and More)

Introduction

As the demand for 5G communications, wearable technology, and high-performance computing accelerates, PCB design is being pushed to its physical limits: lighter, thinner, shorter, and smaller. High-Density Interconnect (HDI) technology has become the core enabler for achieving these goals.

However, an HDI PCB is defined by more than just finer traces. Its foundation lies in the Stackup Design. A well-engineered stackup not only determines manufacturability and cost but also plays a pivotal role in Signal Integrity (SI) and Power Integrity (PI).

This article analyzes common HDI stackup types—such as 1+N+1 and 2+N+2—based on the latest IPC-2226 standards, helping you make informed decisions for your next complex design project.

Table of Contents

1. 1. Introduction
2. 2. What is an HDI Stackup?
3. 3. IPC-2226 Classification of HDI Types
4. 4. Type I: The 1+N+1 Structure
5. 5. Type II: Improved 1+N+1 with Buried Vias
6. 6. Type III: The 2+N+2 Structure
7. 7. Type IV & Advanced: ELIC (Every Layer Interconnect)
8. 8. Engineering Deep Dive: Critical Factors Affecting Yield
9. 9. 2026 Outlook: Materials and Sustainability
10. 10. Summary: Selecting the Right Stackup
11. 11. HDI Stackup FAQ: Insights from the Manufacturing Floor

As the demand for 5G communications, wearable technology, and high-performance computing accelerates, PCB design is being pushed to its physical limits: lighter, thinner, shorter, and smaller. High-Density Interconnect (HDI) technology has become the core enabler for achieving these goals.

However, an HDI PCB is defined by more than just finer traces. Its foundation lies in the Stackup Design. A well-engineered stackup not only determines manufacturability and cost but also plays a pivotal role in Signal Integrity (SI) and Power Integrity (PI).

This article analyzes common HDI stackup types—such as 1+N+1 and 2+N+2—based on the latest IPC-2226 standards, helping you make informed decisions for your next complex design project.

What is an HDI Stackup?

HDI stackups rely primarily on Microvias to achieve interlayer connectivity. Unlike traditional through-hole boards, HDI utilizes laser drilling technology to create minute blind and buried vias, significantly increasing routing density.

In industry terminology, the formula i + N + i is commonly used to describe HDI structures:

• i: Represents the number of build-up layers added to each side of the core. This typically corresponds to the number of laser via tiers.
• N: Represents the number of layers in the central core (usually connected via mechanically drilled through-holes or buried vias).

For a comprehensive understanding of HDI definitions and benefits, please refer to our detailed guide: What is HDI PCB?

IPC-2226 Classification of HDI Types

The IPC-2226 standard categorizes HDI products into six primary types (Type I through Type VI). In practical engineering applications, Type I, Type II, and Type III are the most prevalent, corresponding to what is commonly known as single-build (1-step), double-build (2-step), and multi-build HDI.

1. Type I: 1+N+1 Structure (Single Build-up)

Structure Description:
This is the entry-level form of HDI. It consists of a central laminated core with one build-up layer laminated on both the top and bottom.

• Blind Vias: Connect only the outer layer (L1) to the next adjacent layer (L2).
• Through Vias: Penetrate the entire PCB (L1 to Ln), typically drilled mechanically.
• Limitations: While the standard Type I definition generally excludes buried vias, some manufacturing variations allow for buried vias in the core, provided the blind vias do not stack directly on top of them.

Typical Type I (1+N+1) HDI PCB stackup illustrating blind vias between the outer layers and the laminated core, commonly used for mid-density BGA fan-out designs.

Advantages:

• Relatively low manufacturing cost.
• Mature process with high production yield.
• Suitable for designs with BGA pitch between 0.65mm and 0.8mm.

Applications:
Mid-range smartphone motherboards, handheld GPS devices, and basic control modules.

2. Type II: Improved 1+N+1 with Buried Vias

Structure Description:
The primary distinction between Type II and Type I lies in the treatment of the Core. Type II allows for Buried Vias within the core. These vias are typically filled with resin and plated over (Via-in-Pad process), allowing the surface blind vias to land directly on the buried via pads (if process capabilities permit) or to be staggered.

Type II HDI PCB structure featuring buried vias inside the core, enabling higher routing density and improved power and ground plane continuity.

Key Features:

• Increased Routing Density: Buried vias free up routing space on the outer layers.
• Ground/Power Plane Continuity: Improved inner-layer interconnectivity helps enhance power integrity.

3. Type III: 2+N+2 Structure (Double Build-up)

Structure Description:
When design density increases to a point where a single build-up layer is insufficient, Type III structures are employed. This involves laminating build-up layers twice on both sides of the core.

• Structure: Contains two or more tiers of microvias.
• Blind Via Connections: Can connect L1-L2 and L2-L3.

2+N+2 HDI PCB stackup with double build-up layers on both sides of the core, supporting multi-tier microvias for high-density interconnect routing.

• Stacking Methods:

1. - Staggered Vias: The second-tier blind vias are offset from the first-tier vias. This process is simpler to manufacture.

Staggered microvia configuration in a Type III HDI PCB, offering improved manufacturability and reliability compared to fully stacked vias.

1. - Stacked Vias: The second-tier blind vias are placed directly on top of the first-tier vias. This requires extreme registration accuracy and copper filling capabilities but maximizes space efficiency.

Advantages:

• Extremely high routing density, supporting BGA pitches of 0.4mm or smaller.
• Shorter signal paths, which is beneficial for High-Speed PCB Design.

Applications:
High-end 5G smartphones, AI acceleration cards, DDR4/DDR5 memory modules, and medical devices with strict size constraints.

4. Type IV & Advanced: ELIC (Every Layer Interconnect)

As technology evolves, the traditional distinction between "Core" and "Build-up" has blurred in ultra-high-end applications, evolving into ELIC (Every Layer Interconnect). In this structure, the board lacks traditional mechanical through-holes; all interlayer connections are achieved via stacked laser microvias, allowing for interconnections between any two layers.

ELIC (Every Layer Interconnect) PCB structure where all layers are interconnected using stacked laser-drilled microvias without traditional through-holes.

Advanced multi-step HDI PCB structure showing three-tier stacked microvias, typically used in ultra-high-density and fine-pitch BGA applications.

Why is it Expensive? 

ELIC is not merely a stacking of layers; it pushes manufacturing capabilities to their absolute limits.

1. Registration Tolerance Accumulation:
   Since all connections rely on laser blind vias, layer-to-layer alignment accuracy is critical. As the layer count increases, alignment deviations caused by material expansion and contraction accumulate. Ensuring that L1 connects accurately to L10 imposes rigorous demands on the registration systems of production equipment.
2. Dependency on Advanced Inspection (AOI / X-ray):
   An ELIC board may contain millions of microvias. Traditional electrical testing cannot fully detect all potential latent defects. Consequently, high-precision AOI (Automated Optical Inspection) is mandatory after every build-up layer, and internal stacked vias often require X-ray sampling, significantly increasing cycle time and cost.
3. Non-linear Impact of Yield on Cost:
   ELIC utilizes sequential lamination. If a board requires 10 lamination cycles, a defect occurring in the 9th cycle (such as blistering or drill misalignment) renders the investment in the previous 9 cycles—materials, labor, and machine time—completely wasted. This cumulative risk to yield is the primary driver behind the high cost of ELIC.

Engineering Deep Dive: Critical Factors Affecting Yield

When selecting an HDI stackup, experienced engineers look beyond "layer counts" and "via sizes." They examine physical constraints that can silently derail mass production. The following factors are critical to design success:

1. Laser Aperture vs. Copper Thickness

High-end HDI PCB interconnect technologies including copper-filled vias, conductive paste-filled vias, and copper pillar structures for enhanced reliability.

Laser drilling is constrained by physics. The thicker the copper foil, the higher the energy required for the laser to penetrate it.

• Risk: If the inner layer copper thickness exceeds 1oz, the high energy required for laser drilling can generate excessive heat, resulting in an inverted trapezoidal hole shape or causing "undercut" (erosion of the copper pad at the base).
• Recommendation: For HDI build-up layers, it is advisable to use thinner copper foils (1/3oz or 1/2oz) to ensure an optimal Aspect Ratio for the microvias.

2. Lamination Cycles and Warpage Management

Type III or ELIC structures undergo multiple high-temperature, high-pressure lamination cycles.

• Risk: Each lamination cycle releases internal stresses within the material. If there is a mismatch in the Coefficient of Thermal Expansion (CTE) between the core and build-up materials, or if the copper distribution is uneven, the board is highly susceptible to severe bowing or twisting after multiple cycles. This is catastrophic for the assembly of 0.4mm pitch BGAs.

3. Resin Flow and Impedance Control

• Risk: During the lamination process, the resin in the prepreg flows to fill the gaps between copper traces. Improper control of this flow can cause deviations in the final thickness of the dielectric layer.
• Impact: For high-speed signals, even minute variations in dielectric thickness can cause significant impedance discontinuities. Therefore, high-end HDI stackup design requires precise calculation of the balance between copper density and resin flow.

2026 Outlook: Materials and Sustainability

Integration of High-Speed Materials

With signal rates surpassing 25Gbps, standard FR-4 materials may exhibit excessive loss in complex structures like Type III HDI. Consequently, Hybrid Stackups are becoming increasingly popular. This approach involves using high-frequency materials such as Rogers or Panasonic Megtron for critical signal layers, while using standard FR-4 for non-critical layers to balance performance and cost.

NextPCB has fully upgraded its capabilities to support hybrid lamination processes using Rogers high-frequency materials, catering to the needs of 5G and millimeter-wave radar applications.

Sustainability and Miniaturization

Looking ahead, HDI technology will focus increasingly on environmental sustainability and extreme miniaturization. For a deeper analysis of future market and technical directions, please refer to our article: HDI PCB Trends 2026: Innovation, Market, and Sustainability.

Summary: Selecting the Right Stackup

Key Recommendations:

1. Early Consultation: Confirm the HDI process capabilities (e.g., minimum laser aperture, registration accuracy) with your PCB manufacturer at the very beginning of the design phase.
2. Avoid Over-Design: If a 1+N+1 structure suffices for routing, do not force a transition to 2+N+2, as this will unnecessarily inflate costs.
3. Focus on Impedance: Dielectric layers in HDI are typically thin. Precise calculation of trace width is required to match 50Ω/100Ω impedance requirements.

HDI Stackup FAQ: Insights from the Manufacturing Floor

In hardware communities like r/PrintedCircuitBoard, High-Density Interconnect (HDI) is a frequent topic of debate. Most designers understand the "why" of HDI, but the "how"—specifically regarding stackup types like 1+N+1 and 2+N+2—often leads to confusion and unexpected manufacturing costs. As a manufacturer, we’ve gathered the most common questions from the community to help you bridge the gap between a great layout and a manufacturable board.

Q1: What exactly do the numbers in 1+N+1 and 2+N+2 represent?

The numbers essentially count the sequential lamination cycles and laser drilling steps.

• N: The core of the board, usually a standard multi-layer PCB.
• 1: One additional layer of high-density dielectric and copper added to each side of the core, followed by a laser drill (Microvia) cycle.
• 1+N+1: This requires two pressings (one for the core, one for the outer layers).
• 2+N+2: This requires three pressings because the laser-drilled microvias are added and plated in two separate stages to allow for interconnection between the added layers.

Q2: Why does the price jump so significantly when moving from 1+N+1 to 2+N+2?

The price increase isn't just about adding more layers; it’s about process complexity. Each additional "+1" layer represents an entire cycle of lamination, laser drilling, desmear, copper plating (VCP), and imaging. A 2+N+2 board spends significantly more time on the production line. Furthermore, every lamination cycle introduces registration risks. Ensuring that a 0.1mm microvia aligns perfectly across multiple layers requires extreme precision, and the yield risk associated with that precision is factored into the cost.

Q3: Should I use Stacked Vias or Staggered Vias in my 2+N+2 design?

If your design allows for it, Staggered Vias are always the better choice for reliability and cost.

• Staggered Vias: These are offset from each other, distributing thermal stress more evenly across the board. They are easier to manufacture and have a higher tolerance for process variations.
• Stacked Vias: These are vertically aligned. While they save a massive amount of routing space, they require the lower via to be completely filled with copper (Copper Film/Plated Shut) and planarized before the next via is added. This adds cost and increases the risk of "barrel cracking" during thermal cycling.

Q4: What are the practical limits for Trace and Space in an HDI design?

While advanced LDI (Laser Direct Imaging) allows for extreme precision, we recommend staying at or above 3mil / 3mil (0.075mm) for standard HDI projects to maintain high yields and lower costs. We can push down to 2mil / 2mil, but this typically requires specialized thin copper foils and stricter etching controls, which will increase your per-board price.

Q5: At what point is HDI actually mandatory?

You can often avoid HDI by optimizing your fan-out, but it becomes mandatory when:

• BGA Pitch is ≤ 0.5mm: Traditional mechanical drills and pads are simply too large to route signals out of a fine-pitch BGA.
• Strict Form Factor: When designing wearables or ultra-compact IoT devices where the board real estate cannot accommodate standard via sizes.
• Signal Integrity (SI): When you need to eliminate "via stubs" that cause reflections in high-speed signals. Blind microvias are electrically "cleaner" than through-holes.

Q6: What is the most common mistake engineers make in KiCad or Altium for HDI?

The most frequent error is defining a via span that is physically impossible to manufacture in a single cycle. For example, a designer might define a microvia from Layer 1 to Layer 3 in a 1+N+1 stackup. In reality, that span requires a 2+N+2 process or a very deep laser drill that may violate aspect ratio rules. Always check your Drill Pair settings against the manufacturer's lamination sequence before you finish your routing.

At NextPCB, we provide comprehensive HDI manufacturing services ranging from standard 1+N+1 to complex ELIC structures. Leveraging advanced laser drilling equipment and deep expertise in material science, we ensure your designs are realized with precision.

>> This article references the IPC-2226-A Sectional Design Standard for High Density Interconnect (HDI) Printed Boards. 

About the Author

 Stacy Lu

With extensive experience in the PCB and PCBA industry, Stacy has established herself as a professional and dedicated Key Account Manager with an outstanding reputation. She excels at deeply understanding client needs, delivering effective and high-quality communication. Renowned for her meticulousness and reliability, Stacy is skilled at resolving client issues and fully supporting their business objectives.

LinkedIn

Image Disclaimer:

Some images in this article are sourced from the internet and used for technical illustration only. If any copyright issue arises, please contact us for removal or revision.