4-Layer PCB Stackup Design and Impedance Control

1. Table of Contents
2. 1. Overview of the Multilayer PCB Lamination Process
3. 2. Analyzing the Classic 4-Layer PCB Stackup Structure
4. 3. NextPCB Standard Stackup Parameters and Capabilities
5. 4. Mastering Impedance Control: NextPCB Exclusive Tool Tutorial
6. 5. Advanced Routing Optimization Tips for 4-Layer PCBs
7. 6. Frequently Asked Questions (FAQ)

1. Overview of the Multilayer PCB Lamination Process

The lamination process is currently the most widely used manufacturing technology for multilayer PCBs. It utilizes a subtractive process to create the circuit layers. Through a sequence of critical steps—lamination, mechanical drilling, electroless copper deposition (PTH), and copper plating—the circuits on different layers achieve electrical interconnection. Finally, the application of solder mask, surface finishes (such as HASL or ENIG), and silkscreen printing completes the manufacturing of the multilayer PCB.

Manufacturing precision directly dictates the electrical performance of the PCB. For hardware engineers, understanding the mass production capabilities of modern fabrication facilities is the first step in designing a reliable board. Below is a comprehensive table detailing the current industrial manufacturing capabilities for lamination multilayer PCBs.

2. Analyzing the Classic 4-Layer PCB Stackup Structure

A standard 4 layer pcb stackup typically contains 2 signal layers, 1 power plane (Power Layer), and 1 ground plane (Ground Layer). In terms of physical thickness distribution, a 4-layer board can adopt either an "Equal Spacing Distance Structure" or an "Unequal Spacing Distance Structure."

In an equal spacing structure, the larger dielectric thickness between the signal layer and its reference plane results in significantly higher characteristic impedance, often making it difficult to achieve standard targets such as 50Ω without increasing trace width.Conversely, with an unequal spacing structure, the impedance of the routing layers can be specifically designed and controlled to a desired target value (such as 50Ω).

Theoretically, closely spaced power and ground layers provide a decoupling effect due to planar capacitance. However, if the physical distance between the power layer and the ground layer increases (which is common in standard 1.6mm boards), the inter-layer decoupling effect becomes very limited due to the large spacing, and cannot replace the function of discrete decoupling capacitors. Therefore, when designing circuits, it is mandatory to install adequate decoupling capacitors on the signal layer (Top Layer) near the IC power pins.

In a 4-layer board, the utilization of dedicated power and ground reference planes ensures that the physical distance from the signal layer to its reference plane is significantly smaller than in a 2-layer board. This drastically reduces RF (Radio Frequency) radiated energy. Even so, in standard configurations, the distance between the source traces and the return path can sometimes still be too large, making it difficult to perform optimal magnetic flux cancellation for RF currents generated by the circuits.

To mitigate this, engineers can route a ground trace strictly adjacent to critical signal traces on the signal layer. This provides an immediate return path for the RF return current, significantly enhancing the flux cancellation capability. An excellent design example of an unequal spacing 4-layer board consists of the following:

• Top Layer (Layer 1): Signal layer with 1oz copper, primarily used for horizontal routing. The impedance of this layer can be well controlled. With a typical dielectric thickness (e.g., ~0.077 mm) and dielectric constant (~4.3), a trace width of approximately 3–5 mil (0.075–0.13 mm) can achieve a 50Ω single-ended impedance.
• Inner Layer 1 (Layer 2): Ground Plane (GND), 1oz copper.
• Inner Layer 2 (Layer 3): Power Plane (VCC), 1oz copper.
• Bottom Layer (Layer 4): SSignal layer with 1oz copper, primarily used for vertical routing to minimize crosstalk. The impedance is also controllable. Under similar dielectric conditions (e.g., ~0.077 mm, Er ≈ 4.3), a trace width of approximately 3–5 mil (0.075–0.13 mm) can achieve 50Ω single-ended impedance. For differential routing, the spacing should be determined based on the target impedance using an impedance calculator.

3. NextPCB Standard Stackup Parameters and Capabilities

To ensure that the impedance does not deviate when design files are transferred to physical manufacturing, designers must base their standard pcb stackup on the actual materials used by the fabrication plant (e.g., Dielectric Constant Dk, cured thickness). NextPCB provides a wealth of board thickness options (ranging from 0.4mm to 2.5mm) and precisely defines the standard stackup for each thickness.

Below are a few prime examples extracted from the NextPCB manufacturing capabilities (For more stackup options, please refer to the Stackup Query System):

1. Standard 1.6mm 4-Layer Stackup (Most Commonly Used)

1.6mm is the industry standard thickness for the vast majority of consumer and industrial electronic products.

Engineering Perspective: This stackup typically utilizes a Core thickness in the range of approximately 0.8mm to 1.2mm along with 1080 Prepreg (approx. 0.077mm), depending on the fabrication process. It minimizes the L1-L2 and L4-L3 loop inductance. However, because L4's reference plane is L3 (Power), high-frequency return currents will require well-placed bypass capacitors at layer transitions to ensure continuous return paths across the thick central core.

2. Thin 0.8mm 4-Layer Stackup (Ideal for Portables/IoT)

For space-constrained IoT devices or compact modules, 0.8mm is highly recommended.

Engineering Perspective: With the central Core reduced to 0.5mm,the distributed capacitance between the power and ground planes increases significantly due to reduced spacing. This results in a lower overall Power Delivery Network (PDN) impedance compared to a 1.6mm board. It also provides a superior aspect ratio for via drilling.

3. Thick 2.0mm and 2.5mm 4-Layer Stackups (For Backplanes/Industrial/High-Current)

In scenarios requiring high mechanical stress tolerance or deep connector insertions, thicker boards are necessary.

Engineering Perspective: NextPCB achieves 2.0mm and 2.5mm stackups primarily by increasing the internal Core thickness (1.7mm and 2.2mm respectively). Notably, the outer layer Prepreg remains 1080 (0.077mm). This demonstrates rigorous process control: regardless of total board thickness, maintaining consistent Prepreg specifications allows engineers to use the exact same characteristic impedance trace width rules across different projects without redesigning.

>> Rcommend reading: PCB Impedance Control Services | NextPCB

4. Mastering Impedance Control: NextPCB Exclusive Tool Tutorial

In a 4-layer board, ensuring strict impedance matching is vital for signal integrity. To prevent your traces from violating manufacturing tolerances (usually required to be within ±10%), hardware designers must abandon the habit of "guessing trace widths" and utilize precision calculation tools.

Step 1: Obtain Accurate Dielectric Parameters

Avoid blindly trusting the default dielectric constants built into third-party EDA software (like Altium or KiCad). Different material vendors (like Shengyi or KB) have varying Er (Dk) values.

Action: Visit the NextPCB Impedance Control Stackups System.

Here, input your layer count (4 layers), target thickness, and copper weight requirements. The system will generate a standard HQDFM Stack-up report. Note down the exact thickness (H) of the PP and Core, along with their corresponding dielectric constants (Er, usually between 4.2 and 4.6).

Step 2: Calculate Trace Width and Spacing Online

Once you have the parameters, proceed to impedance calculation.

Action: Use the NextPCB PCB Impedance Calculator.

Tutorial:

1. Select Impedance Model: For standard L1/L4 routing, select "Outer Single-ended" (e.g., 50Ω for clocks/antennas) or "Outer Differential" (e.g., 90Ω for USB, 100Ω for Ethernet).
2. Input Target Impedance: Enter your goal, such as 50 ohms.
3. Input Stackup Parameters:
   • - H1 (Dielectric Thickness): Enter the PP thickness obtained in Step 1 (e.g., approx. 0.077mm for 1080 PP).
   • - Er1 (Dielectric Constant): Enter the corresponding material dielectric constant.
   • - T1 (Copper Thickness): Enter the post-plating actual thickness for the outer layer (approx. 0.035mm for 1oz finished).
4. Calculate: The system utilizes an integrated 2D field solver to reverse-engineer and output the required Trace Width (W1/W2) and Spacing (for differential pairs).

Directly input these calculated values into your EDA software's Design Rule Check (DRC). When submitting your Gerber files to NextPCB, always check the "Impedance Control" box in the order notes; the CAM engineering team will perform final micro-adjustments to guarantee perfect performance.

 >> Recommend reading: How to Achieve Controlled Impedance without Increasing Costs

5. Advanced Routing Optimization Tips for 4-Layer PCBs

Even with a perfect 4 layer pcb stackup, poor routing can degrade system performance. Keep these critical guidelines in mind:

1. Maintain Return Path Continuity: Signals on L1 primarily rely on L2 (GND) for their return path, while L4 signals rely on L3 (Power). Never place arbitrary split planes or slots in L2 and L3. If a high-speed signal crosses a split in the reference plane, the return current is forced to detour, creating massive loop inductance and severe EMI radiation.
2. Implement Coplanar Grounding: When the distance between the source trace and the return plane is insufficient to fully cancel RF flux, place a Coplanar Ground trace parallel to critical signals (like clock lines) on L1/L4. Stitch this ground trace to the L2 GND plane with vias at regular intervals to dramatically enhance RF flux cancellation.
3. Address Reference Plane Switching: If a critical signal transitions from L1 to L4 through a via, its reference plane switches from GND to Power. Because high-frequency return currents cannot easily cross the thick 1.2mm Core between GND and Power, they will seek the nearest decoupling capacitor. It is highly recommended to place a 0.1uF stitching capacitor right next to the signal via to bridge the return path across the planes.

6. Frequently Asked Questions (FAQ)

Q1: Why did the fabrication plant modify my impedance trace widths during the engineering confirmation phase?

A: This is a standard industry practice. The trace widths you set in EDA software are often based on ideal dielectric constants or default thicknesses. During actual lamination, the specific Prepreg model (e.g., 1080, 2116) and resin flow rates cause minor thickness variations. To strictly hit your requested 50Ω/90Ω targets, NextPCB's CAM engineers mathematically compensate your trace widths (usually within ±20%) based on real-time material characterization. To minimize these adjustments, always use the NextPCB impedance calculator before routing.

Q2: In a standard 1.6mm 4-layer board, can I place Power and GND on the inner layers (L2/L3), and then pour solid copper polygons on L1 and L4 as additional grounds?

A: Yes, this creates a "Faraday cage" shielding effect. However, be aware of a major pain point: if you pour large copper areas on L1/L4 close to impedance-controlled microstrip lines, it inadvertently creates a Coplanar Waveguide (CPW) model. The proximity of the surface ground copper will alter the fringing capacitance and lower the trace's impedance. You must maintain a significant clearance (typically ≥ 3 times the trace width) between the trace and the poured copper, or explicitly select a "Microstrip with Coplanar Ground" model during your impedance calculations.

Q3: My 4-layer board failed EMI testing, and I noticed many high-speed signals are routed on Layer 4. Is this related to the stackup?

A: Very likely. In a standard stackup, the reference plane for L4 is L3 (Power). High-frequency return currents for L4 traces flow on the power plane. If your Power Delivery Network (PDN) lacks adequate high-frequency decoupling, or if L3 is heavily fragmented by multiple voltage islands, the return path becomes highly resistive and inductive, causing the board to radiate like an antenna. Solution: Route critical clocks and high-frequency RF signals strictly on L1 (referencing the solid L2 GND plane). If you must route on L4, ensure the power plane directly above the trace is solid and unbroken.

Q4: Is it acceptable to use a non-traditional stackup like L1(GND) - L2(Signal) - L3(Signal) - L4(Power) for internal routing?

A: While it can physically be manufactured, it is heavily discouraged from both an electrical and cost perspective. Internal routing means all high-speed lines become striplines sandwiched between planes, requiring complex via transitions just to break out the signals. Furthermore, in standard 4-layer boards, the central Core is thick (e.g., 1.2mm). Traces on L2 and L3 would be very far from their secondary reference planes, making 50-ohm impedance control nearly impossible without using impractically wide traces. Stick to the industry-standard L1(Sig)-L2(GND)-L3(Pwr)-L4(Sig) format to mitigate risks.

Q5: Why do standard 4-layer stackups always prioritize a "symmetrical" structure (e.g., using 1080 PP on both top and bottom)? Can I request an asymmetrical build?

A: PCBs are composite structures of fiberglass and epoxy resin. During the extreme heat of the lamination press (over 180°C) and subsequent cooling, thermal stresses are introduced. If the copper thickness, copper distribution, or dielectric thickness is severely asymmetrical around the central Core, the uneven release of stress will cause severe board warpage. This warpage will destroy coplanarity during SMT assembly, leading to cold soldering or tombstoning of components. NextPCB's standard pcb stackups are rigorously tested for symmetrical stress balance to guarantee high manufacturing yield and reliability.