How GPU PCBs Are Manufactured: From Bare Board to Final PCBA

Introduction

A GPU PCB for an AI server is not manufactured the way a consumer electronics board is manufactured. The stack of processes required to take a 32-layer, low-loss laminate baseboard from raw material to a fully assembled PCBA carrying eight H100 GPUs, four NVSwitch chips, and hundreds of power management components involves more than twenty discrete manufacturing steps, each of which must be executed within tight tolerances for the finished board to meet its signal integrity, power delivery, and reliability specifications.

Understanding the manufacturing sequence matters for engineers on both sides of the design-to-production handoff. For PCB designers, knowledge of the manufacturing process informs decisions about via structures, copper weight, surface finish, and test access that cannot be changed after the board is in production. For procurement and program managers, it sets realistic expectations for lead time, yield, and the cost drivers of complex AI server boards.

This article walks through the complete GPU PCB manufacturing sequence, from the first design file review through final functional test, with specific attention to the process steps that differ between standard commercial PCBs and the high-complexity boards required by modern AI accelerator hardware.

1. Table of Contents
2. Introduction
3. What Makes a GPU PCB Different
4. Step 0: Design Inputs and Pre-Production Engineering
5. Gerber Files and ODB++
6. Stackup Definition and Material Specification
7. Design Rule Check and DFM Review
8. Step 1: Inner Layer Fabrication
9. Laminate Preparation
10. Photolithographic Imaging
11. Copper Etching
12. Automated Optical Inspection (Inner Layers)
13. Step 2: Sequential Lamination
14. Black or Brown Oxide Treatment
15. Layup and Registration
16. Press Cycle
17. HDI Build-Up Lamination
18. Step 3: Drilling
19. Mechanical Drilling (Through-Holes)
20. Laser Drilling (Microvias)
21. Controlled-Depth Backdrilling
22. Step 4: Copper Plating
23. Desmear and Activation
24. Electroless Copper Deposition
25. Electrolytic Copper Plating
26. Via Fill and Planarization
27. Step 5: Outer Layer Imaging and Etching
28. Step 6: Surface Finish
29. ENIG (Electroless Nickel Immersion Gold)
30. ENEPIG
31. OSP (Organic Solderability Preservative)
32. Hard Gold for Edge Connectors
33. Step 7: Solder Mask Application
34. Step 8: Silkscreen and Legend Printing
35. Step 9: Electrical Testing of Bare Board
36. Step 10: Impedance and Signal Integrity Verification
37. Step 11: Profiling, V-Score, and Final Bare Board Inspection
38. Step 12: SMT Assembly — Paste Printing
39. Step 13: Component Placement
40. Step 14: Reflow Soldering
41. Step 15: Automated Optical Inspection (Post-Reflow)
42. Step 16: X-Ray Inspection for BGA and Hidden Joints
43. Step 17: Press-Fit Connector Assembly
44. Step 18: Functional Test and Burn-In
45. Quality Standards for GPU PCBs
46. FAQ

---

What Makes a GPU PCB Different

Before describing the manufacturing sequence, it is worth summarizing the characteristics that distinguish GPU and AI accelerator PCBs from standard commercial boards. These characteristics determine which manufacturing steps are required, which tolerances are critical, and which process capabilities a fabricator must have to produce the board reliably.

Characteristic	Standard Commercial PCB	GPU / AI Accelerator PCB
Layer count	4–12	16–40+
Laminate material	Standard FR4	Low-loss (Megtron 6/7, Tachyon 100G, Rogers)
Copper foil	Standard ED copper	VLP or HVLP copper on signal layers
Via types	Through-hole only (most designs)	Through-hole + laser microvias + backdrilled stubs + via-in-pad
Lamination cycles	1 (single press)	3–5 (sequential lamination for HDI build-up)
Minimum trace/space	100 μm / 100 μm	75 μm / 75 μm (signal layers); finer on BGA escape
Controlled impedance tolerance	± 10%	± 5%
Copper weight (power planes)	1 oz (35 μm)	2–3 oz (70–105 μm)
Surface finish	HASL or ENIG	ENIG or ENEPIG (BGA pads); hard gold (edge connectors)
BGA complexity	Standard pitch (≥ 0.8 mm)	Fine-pitch (0.65–0.8 mm); large die (40–60 mm package)
Electrical test	Flying probe or bed-of-nails	Flying probe + TDR impedance + network analyzer channel verification
Post-assembly inspection	AOI	AOI + 3D X-ray (BGA) + functional burn-in

For a detailed breakdown of why GPU PCBs require these specifications, see AI Accelerator PCB Design Guide: Layers, Materials and Signal Integrity for H100/H200 Boards.

---

Step 0: Design Inputs and Pre-Production Engineering

Gerber Files and ODB++

Manufacturing begins with the transfer of design data from the EDA tool to the fabricator. The standard formats are:

• Gerber RS-274X: Individual layer files describing copper geometry, drill patterns, solder mask, and legend; the most widely supported format
• ODB++: A richer data format that captures netlist connectivity, component placement, and layer stackup in a single package; preferred by advanced fabricators for DFM analysis and test program generation
• IPC-2581: An emerging standard combining the completeness of ODB++ with open, non-proprietary data exchange; increasingly adopted for complex boards

For GPU PCBs, the design data package also includes: the impedance specification document (target impedance values and tolerances for each controlled impedance structure), the stackup document (dielectric thickness, material grades, copper weight per layer), the drill file with depth specifications for backdrilled vias, and any special process notes (copper coin requirements, thermal via arrays, edge connector gold specifications).

Stackup Definition and Material Specification

The fabricator's process engineering team translates the designer's stackup specification into a manufacturable build using the actual dielectric thicknesses and copper weights available in their material inventory. Key considerations:

• Prepreg resin content affects dielectric thickness after pressing—the fabricator must select prepreg combinations that achieve the specified post-press dielectric thickness within the impedance tolerance budget
• Low-loss laminates (Megtron 6/7, Tachyon 100G) have specific press cycle requirements (temperature, pressure, dwell time) that differ from standard FR4; the fabricator must have qualified press cycles for each material system
• Hybrid stackups (mixing low-loss material on signal layers with standard material on power/ground layers) require verification that the bonding chemistry between dissimilar materials is compatible and that CTE (coefficient of thermal expansion) mismatch does not cause delamination under thermal cycling

Design Rule Check and DFM Review

Before releasing the job to the production floor, the fabricator's engineering team runs the design through:

• Electrical design rule check (DRC): Verifies minimum trace/space, annular ring, drill-to-copper clearance, and other geometric constraints against the fabricator's process capabilities
• DFM (Design for Manufacturability) review: Identifies features that are at or beyond process limits: via-in-pad without specified fill, trace widths that cannot be held to impedance tolerance, or backdrilling depths that conflict with stackup geometry
• Netlist extraction and test program generation: For electrical testing, the netlist is extracted from the design data and used to generate flying probe programs or bed-of-nails test fixtures

---

Step 1: Inner Layer Fabrication

Laminate Preparation

Inner layer cores (thin sheets of cured laminate pre-clad with copper foil on both sides) are cut from master panels to the working panel size. For GPU PCBs using low-loss laminates:

• Material is stored in temperature- and humidity-controlled environments (typically 20–25°C, < 50% RH) to prevent moisture absorption that would affect dielectric properties and bond strength
• Panel surfaces are cleaned (brushing + chemical cleaning) immediately before imaging to remove surface oxides and contaminants that would degrade photoresist adhesion
• Very-low-profile (VLP) and HVLP copper foils, used on NVLink signal layers, have lower surface roughness than standard ED copper; this affects cleaning parameters and resist adhesion protocols

Photolithographic Imaging

The copper layer pattern is transferred to the laminate using photolithography:

1. Dry film photoresist lamination: A photosensitive film is laminated to the copper surface under controlled temperature and pressure
2. Exposure: A UV light source exposes the resist through a photomask (for older processes) or directly via laser direct imaging (LDI); LDI is preferred for fine-pitch GPU PCB features because it eliminates registration errors from film-based masks and achieves ± 5 μm line width accuracy
3. Development: The unexposed resist is dissolved in a developer solution, leaving resist only where copper should remain

For GPU PCB inner layers with 75–100 μm trace widths and spaces, LDI is essentially mandatory to achieve the line width uniformity required for ± 5% impedance tolerance.

Copper Etching

Exposed copper (not protected by photoresist) is removed by chemical etching, leaving the defined circuit pattern. Etch chemistry and process parameters are tightly controlled:

• Etchant type: Alkaline ammoniacal etchant is standard for copper etching in multilayer PCB production; etch rate must be uniform across the panel to avoid over- or under-etching at panel edges vs center
• Etch factor: The ratio of etch depth to undercut beneath the resist; higher etch factor (more vertical sidewalls) is required for fine-pitch traces to maintain the as-designed trace width; etch factor is a key process parameter for GPU PCB fabricators
• Resist stripping: After etching, the photoresist is chemically stripped, leaving bare copper traces

Automated Optical Inspection (Inner Layers)

Every inner layer is inspected by AOI before lamination. AOI systems use high-resolution cameras and pattern-matching algorithms to detect:

• Opens (broken traces) and shorts (unintended copper bridges)
• Trace width violations (too narrow or too wide, which directly affects impedance)
• Missing or extra copper features
• Pit or scratch defects in the copper surface

For GPU PCBs, AOI resolution must be fine enough to detect trace width deviations of ± 5 μm on 75–100 μm traces. Defective inner layers are scrapped before lamination; a defect found after lamination in a 28-layer board represents far more lost material and processing cost than a defect found at the inner layer stage.

---

Step 2: Sequential Lamination

Black or Brown Oxide Treatment

Before lamination, inner layer copper surfaces are treated with a chemical oxidation process (black oxide or brown oxide / bond enhancement alternatives) to roughen the copper surface at the microscopic level. This increases the mechanical bond strength between copper and the prepreg resin that will flow around and adhere to the copper during pressing. For VLP and HVLP copper foils used on GPU PCB signal layers, the oxidation parameters must be carefully controlled to avoid over-roughening the already-smooth surface.

Layup and Registration

Inner layer cores, prepreg sheets, and outer copper foils are stacked in the correct order in a registration fixture. For a 28-layer GPU PCB with 2+N+2 HDI:

• The core stack (N layers) is assembled first from individual inner layer cores and prepreg sheets
• Registration pins through tooling holes ensure each layer is precisely aligned; layer-to-layer registration accuracy must be ± 50 μm across the full panel to meet via alignment requirements
• Copper foil sheets are placed on the top and bottom of the stack to become the outermost copper layers of the core

Press Cycle

The layup is placed in a hydraulic lamination press. Heat and pressure cause the prepreg resin to flow, wet the copper surfaces, and cure into a solid dielectric. Key process parameters:

• Temperature: Ramp rate and peak temperature are material-specific; Megtron 6 and Tachyon 100G require different peak temperatures and dwell times than standard FR4; incorrect press cycles cause incomplete cure (low T_g), resin starvation (thin dielectrics), or resin pooling (thick dielectrics)
• Pressure: Applied uniformly across the panel; non-uniform pressure causes dielectric thickness variation that directly translates to impedance variation
• Vacuum: Applied during press cycle to remove trapped air and volatiles; voids in the dielectric create impedance discontinuities and reduce insulation resistance
• Duration: Sufficient dwell at cure temperature to achieve full resin polymerization; under-cured resin has reduced T_g and increased moisture absorption

HDI Build-Up Lamination

For GPU PCBs using HDI structures (1+N+1, 2+N+2, or any-layer), additional lamination cycles are required after the core is pressed and drilled. Each build-up cycle adds one or two additional layers to each side of the core:

• The pressed and drilled core is cleaned, treated, and returned to the lay-up area
• Thin prepreg (RCC—Resin-Coated Copper, or thin prepreg with copper foil) is added on each side
• The stack is pressed again, adding the build-up layer(s)
• Laser drilling of microvias follows each build-up lamination cycle
• A 2+N+2 HDI board requires three total lamination cycles (one for core, two for build-up layers); a 3+N+3 board requires four

---

Step 3: Drilling

Mechanical Drilling (Through-Holes)

After core lamination (before HDI build-up), through-holes are drilled using CNC drill machines with carbide drill bits. For GPU PCBs:

• Minimum mechanical drill diameter: typically 100–150 μm for buried vias in the core; 200–300 μm for through-hole vias in the finished board
• Drill position accuracy: ± 25–50 μm from nominal center; larger position errors reduce annular ring and risk shorts to adjacent copper features
• Entry and exit material (aluminum entry foil, phenolic backup board) controls burr formation at the drill entry and exit faces
• Drill bit changes at specified hit counts to prevent tool wear-induced hole quality degradation; worn bits cause rough hole walls that reduce plating adhesion and increase insertion loss on high-speed signal vias

Laser Drilling (Microvias)

HDI microvias (75–150 μm diameter) are drilled using CO₂ or UV laser systems after each build-up lamination cycle:

• CO₂ laser: Used for drilling through dielectric to a copper target pad; the laser ablates the resin but is stopped by the copper target pad (copper reflects CO₂ wavelengths); suitable for standard microvia drilling
• UV laser (Nd:YAG or excimer): Can drill through both resin and thin copper; used for conformal mask drilling (where the top copper is patterned to define the via aperture) and for very small vias where CO₂ beam size is too large
• Stacked via drilling: For any-layer HDI (ELIC), microvias from multiple build-up cycles are stacked directly on top of each other; alignment of successive laser drilling cycles must be within ± 25 μm to ensure the stacked vias form a clean electrical connection through all layers

Controlled-Depth Backdrilling

Backdrilling is a critical process step for GPU PCBs carrying NVLink 4.0/5.0 and PCIe Gen5/6 signals. Via stubs—the unused portion of a through-hole via below the deepest signal connection point—act as stubs that resonate at high frequencies and degrade signal integrity. Backdrilling removes these stubs by drilling from the opposite side of the board to a precisely controlled depth.

• Drill depth control: The backdrill must remove the stub without cutting into the signal connection; depth accuracy requirement is typically ± 50 μm; CNC machines with depth feedback (measuring Z-axis position against the panel surface) are required
• Backdrill diameter: Larger than the original via drill (typically original diameter + 200–400 μm) to ensure complete stub removal including the plating on the original via wall
• Per-panel drill files: Because actual dielectric thickness after pressing varies panel-to-panel by ± 3–5%, backdrill depth files should be generated from measurements of the actual as-built stackup thickness of each panel, not from the nominal stackup specification
• Stub verification: Post-backdrill cross-section or TDR measurement on representative test coupons verifies that stub length meets the specification (< 10 mils for NVLink 4.0; < 5 mils for NVLink 5.0)

---

Step 4: Copper Plating

Desmear and Activation

After drilling, the hole walls contain resin smear from the drilling process and the glass fiber reinforcement of the laminate. Desmear removes this contamination by chemical treatment (permanganate-based or plasma), exposing clean resin and glass surfaces that can bond to the subsequently deposited copper. For high-speed GPU PCBs, thorough desmear is especially important because resin smear on via walls creates high-resistance spots that increase via insertion loss.

Electroless Copper Deposition

After desmear and chemical activation (palladium catalyst deposition), a thin layer of copper (1–3 μm) is deposited on all exposed surfaces including via walls by autocatalytic electroless plating. This creates the conductive seed layer required for subsequent electrolytic plating. Electroless copper quality—uniformity, adhesion, and coverage in deep via holes—directly affects the reliability of the finished via.

Electrolytic Copper Plating

Electrolytic (electroplated) copper builds the via wall thickness to specification—typically 25 μm minimum in the finished via. For GPU PCBs:

• Plating bath chemistry and agitation must provide uniform throw into high-aspect-ratio vias (aspect ratio = board thickness / via diameter; a 3.2 mm thick board with 200 μm vias has aspect ratio 16:1—at the upper limit of reliable plating)
• Panel plating (plating the entire panel surface) followed by pattern plating (additional plating in the patterned trace areas) is the standard process; panel plating ensures adequate via wall coverage before pattern plating builds trace thickness
• Heavy copper layers (2–3 oz on power planes) require extended plating time or multiple plating cycles; the plating process must be uniform across the panel to avoid excessive copper on panel edges and thin copper at the center

Via Fill and Planarization

For via-in-pad (VIPPO) structures on GPU PCBs—where vias are placed directly within BGA pads to maximize routing density under fine-pitch GPU packages—the plated vias must be filled with epoxy and planarized before the outer layer copper is patterned:

• Conductive epoxy fill: Silver-filled conductive epoxy is screen-printed or vacuum-filled into the via openings; provides electrical continuity through the fill as a backup to the via wall plating
• Non-conductive epoxy fill: Resin-based fill for vias where conductivity through the fill is not required; lower cost than conductive fill but must be used with appropriate design intent
• Curing: Filled vias are cured in an oven; cure shrinkage must be controlled to prevent dimpling of the fill surface below the pad level
• Planarization (grinding): The cured fill is mechanically ground flush with the copper pad surface to within < 10 μm planarity; dimensional accuracy here directly affects solder paste volume and solder joint quality in the subsequent BGA assembly step
• Cap plating: Additional copper is electroplated over the filled and planarized via to create a solid, flat pad surface; cap plating thickness must be uniform and free of pinholes

---

Step 5: Outer Layer Imaging and Etching

After the core (and any build-up layers) are plated, the outer layer copper is patterned using the same photolithographic process as the inner layers. For GPU PCBs, outer layer features include:

• BGA pad arrays for GPU, NVSwitch, VRM, and other component packages
• SMT pads for passive components (capacitors, resistors, ferrite beads)
• Press-fit connector holes (for power connectors, if applicable)
• Test points for flying probe access
• Ground plane copper pours with thermal relief patterns for through-hole components

Outer layer etching must achieve the same ± 5 μm trace width accuracy as inner layers, as outer layer trace widths contribute to controlled impedance on microstrip structures (traces on the outer layer referenced to an adjacent inner ground plane).

---

Step 6: Surface Finish

ENIG (Electroless Nickel Immersion Gold)

ENIG is the dominant surface finish for GPU PCB BGA pads. The process deposits a layer of electroless nickel (3–6 μm) followed by a thin immersion gold layer (0.05–0.1 μm). The nickel layer provides a solderable surface and a diffusion barrier preventing copper from migrating into the solder joint; the gold layer prevents nickel oxidation during storage.

ENIG quality is critical for fine-pitch BGA assembly. Black pad defect (excessive nickel corrosion during the gold immersion step) creates a weak solder joint that may pass initial inspection but fail in service. GPU PCB fabricators must control ENIG bath chemistry (phosphorus content in the nickel, gold bath pH and temperature) within tight limits to prevent black pad formation on high-value boards carrying GPU and NVSwitch packages.

ENEPIG

Electroless Nickel Electroless Palladium Immersion Gold adds a palladium interlayer between the nickel and gold. The palladium layer provides better wire-bondability (relevant for some AI accelerator module designs), more robust solderability after multiple reflow cycles, and greater resistance to black pad defect. ENEPIG is specified on some GPU accelerator module PCBs where reliability requirements are more stringent than standard ENIG can guarantee.

OSP (Organic Solderability Preservative)

OSP applies a thin organic coating to bare copper pads to prevent oxidation during storage. It is lower cost than ENIG and provides an excellent coplanar surface for fine-pitch SMT. OSP is sometimes used on GPU PCB areas that will be soldered immediately after manufacture (not requiring long storage) and where the area is not subject to multiple reflow cycles. For BGA pads on high-complexity GPU boards, ENIG or ENEPIG is generally preferred over OSP for reliability.

Hard Gold for Edge Connectors

GPU baseboard and OAM module edge connectors (NVLink connectors, OAM edge card contacts, PCIe edge card contacts) require hard gold plating (electroplated gold with cobalt or nickel alloy, 0.76–1.27 μm) over an electrolytic nickel underlayer. Hard gold provides the wear resistance required for connectors that are mated and unmated repeatedly. The gold plating specification (thickness, alloy composition, hardness) is defined by the connector standard and verified by thickness measurement (XRF spectroscopy) at incoming inspection.

---

Step 7: Solder Mask Application

Liquid photoimageable (LPI) solder mask is applied to the board surface, exposed through a photomask or by LDI, developed, and cured. Solder mask covers all copper surfaces except SMT pads and through-hole pad rings, preventing solder bridging during assembly and protecting copper from oxidation in service.

For GPU PCBs with fine-pitch BGA pads:

• Solder mask defined (SMD) vs non-solder-mask-defined (NSMD) pads: NSMD pads (where the solder mask opening is larger than the copper pad) are preferred for fine-pitch BGA assembly because they allow the solder to wet the full copper pad perimeter, forming a stronger fillet; SMD pads (mask opening smaller than pad) are used where pad diameter is the dimensional reference for the solder joint
• Registration accuracy: Solder mask opening registration to copper pads must be ± 25–50 μm for fine-pitch BGA arrays; misregistration can partially cover BGA pads and cause insufficient solder volume or poor wetting
• Via tent-and-fill: Non-signal vias in copper pour areas are typically tented (covered) with solder mask to prevent solder wicking during assembly; via-in-pad structures are covered with filled and planarized epoxy as described in Step 4, not solder mask

---

Step 8: Silkscreen and Legend Printing

Component reference designators, polarity markers, board identification, and other legend information are printed in white (or another color) ink on the solder mask surface by inkjet or screen printing. For GPU PCBs, silkscreen is a relatively minor step but must not intrude on SMT pad areas or BGA pad arrays where ink contamination would affect solderability.

---

Step 9: Electrical Testing of Bare Board

Before shipping to assembly, the bare PCB undergoes electrical testing to verify continuity and isolation:

• Flying probe testing: Movable probe heads contact test points and measure resistance between all net connections; verifies opens (broken traces, missing via plating) and shorts (unintended connections between nets); standard for prototype and low-volume GPU PCBs where fixture cost is not justified
• Bed-of-nails testing: A fixed fixture with spring-loaded pins contacts all test points simultaneously; faster than flying probe for high-volume production but requires a board-specific fixture (cost: $5,000–$30,000 depending on pin count and complexity)
• High-potential (Hi-Pot) testing: Applies elevated voltage between selected nets to verify dielectric integrity; particularly important for high-voltage isolation requirements between 48 V power rails and signal nets on OAM UBB designs

---

Step 10: Impedance and Signal Integrity Verification

Controlled impedance structures on GPU PCBs are verified using Time Domain Reflectometry (TDR) on representative test coupons fabricated alongside the production boards on the same panel:

• TDR coupon design: Coupons include microstrip and stripline structures representative of the critical high-speed traces in the design (NVLink differential pairs, PCIe Gen5 lanes); coupon trace length is typically 15–20 cm for adequate TDR resolution
• Measurement: A TDR instrument applies a fast step edge signal and measures the reflection coefficient vs time; impedance discontinuities appear as deviations from the target impedance value
• Acceptance criterion: Impedance within ± 5% of target across the coupon length; points outside tolerance cause the lot to be reviewed and potentially scrapped
• Network analyzer (VNA) testing: For the highest-confidence signal integrity verification, insertion loss (S₂₁) and return loss (S₁₁) are measured on channel coupons using a vector network analyzer; this verifies not just impedance but actual channel loss at the NVLink 4.0 / PCIe Gen5 operating frequencies

---

Step 11: Profiling, V-Score, and Final Bare Board Inspection

The finished panel is routed to the final board outline (profiling) using CNC routing, or V-scored for arrays that will be depaneled after assembly. A final visual and dimensional inspection verifies:

• Board dimensions and hole locations within drawing tolerances
• Surface finish appearance (no bare copper, no mask bleed onto pads)
• Edge connector gold plating coverage and quality
• Board warpage and twist (< 0.75% of diagonal length per IPC-6012 Class 3 requirements)

---

Step 12: SMT Assembly — Paste Printing

Assembly begins with solder paste printing. A stainless steel stencil with apertures matching the SMT pad pattern is aligned to the board, and solder paste is squeegeed through the apertures onto the pads. For GPU PCBs:

• Stencil thickness: Typically 100–150 μm for standard SMT pads; reduced to 100 μm or less for fine-pitch BGA areas to prevent paste bridging between adjacent pads
• Aperture design: BGA pad apertures are typically 80–90% of the pad diameter to control paste volume and prevent bridging; fine-pitch pads (< 0.5 mm pitch) may use step stencils with localized thickness reduction
• Paste inspection (SPI): 3D solder paste inspection systems measure paste volume, height, and area coverage on every pad after printing; paste volume deviation > ± 25% from target on BGA pads triggers a board-level reject before component placement

---

Step 13: Component Placement

Pick-and-place machines retrieve components from tape-and-reel feeders or trays and place them onto the solder paste with ± 25–50 μm placement accuracy. For GPU PCBs:

• GPU / NVSwitch BGA placement: Large packages (40–60 mm) are placed by gantry-type machines with vision-based fiducial alignment; placement accuracy is critical because misalignment of > 50% of pad pitch causes solder bridging or insufficient pad coverage after reflow
• Tray-fed components: Large BGAs, GPU modules, and NVSwitch packages are typically supplied in trays rather than tape-and-reel; tray handling requires additional machine tooling and slows placement throughput vs tape-fed passives
• Passive component placement: Hundreds of decoupling capacitors, VRM inductors, and resistors are placed at high speed by dedicated SMT machines; placement order is optimized to minimize head travel distance and maximize throughput

---

Step 14: Reflow Soldering

The populated board passes through a reflow oven where the solder paste melts and forms solder joints between component leads/balls and PCB pads. Reflow profile design is critical for GPU PCBs:

• Preheat zone: Ramps board temperature from ambient to ~150°C to activate flux and drive off solvents; ramp rate typically 1–3°C/s to avoid thermal shock to large BGA packages and PCB laminate
• Soak zone: Holds at 150–180°C for 60–90 seconds to equalize temperature across the board and activate flux chemistry; GPU baseboards with large thermal mass (heavy copper planes, large BGA packages) require longer soak times to prevent temperature gradients between thick and thin areas
• Reflow zone: Ramps to peak temperature (typically 235–250°C for SAC305 lead-free solder); time above liquidus (TAL, typically 183°C for SAC305) should be 45–90 seconds; insufficient TAL causes incomplete solder melting and cold joints; excessive TAL causes solder joint grain coarsening and long-term reliability degradation
• Cooling zone: Controlled cooling at 3–6°C/s; faster cooling increases solder joint fatigue resistance (finer grain structure) but excessive cooling causes warpage-driven solder joint opens on large BGA packages
• Nitrogen atmosphere: Reflow in nitrogen (O₂ < 100 ppm) reduces oxidation of solder and pad surfaces, improving solder joint quality and enabling the use of lower-activity (ROL0) flux; recommended for fine-pitch BGA GPU assemblies

---

Step 15: Automated Optical Inspection (Post-Reflow)

After reflow, AOI systems inspect the assembled board for:

• Missing or wrong-value components (by comparing component color, shape, and marking to the assembly database)
• Lifted components, skewed placement, and tombstoning on small passive components
• Solder bridges between adjacent fine-pitch pads
• Insufficient solder on exposed pads (side terminations on QFN and similar packages)

AOI cannot inspect the underside of BGA packages—the solder joints are hidden beneath the package body. This is why X-ray inspection is mandatory for all BGA packages on GPU PCBs.

---

Step 16: X-Ray Inspection for BGA and Hidden Joints

2D and 3D X-ray inspection (AXI—Automated X-ray Inspection) is essential for verifying BGA solder joint quality on GPU, NVSwitch, and other BGA components:

• 2D X-ray: Provides a top-down view of BGA ball array; reveals bridging, missing balls, and severe voids; does not distinguish between balls in different layers of a stacked BGA
• 3D computed tomography (CT X-ray): Reconstructs a 3D volume of the BGA from multiple 2D projections at different angles; reveals internal voids, partial bridges, and solder ball deformation that 2D X-ray cannot detect; preferred for high-reliability GPU PCB inspection
• Void acceptance criteria: IPC-7095 and customer-specific specifications define the maximum allowable void area as a percentage of ball cross-section; typical acceptance for AI server BGAs is < 25% void area per ball, with no voids in more than 10% of balls in a package
• 100% inspection: Every GPU, NVSwitch, and VRM BGA package on a GPU PCB should be X-ray inspected; statistical sampling is not appropriate for high-value assemblies where a single failing BGA joint would cause board-level failure

---

Step 17: Press-Fit Connector Assembly

High-current power connectors on GPU baseboards and OAM UBBs are often press-fit (compliant pin connectors) rather than soldered, because their large thermal mass makes reliable solder reflow difficult and their mechanical stress during mating requires the additional retention of press-fit engagement. Press-fit assembly requires:

• Precisely drilled and plated through-holes within the connector's press-fit pin diameter tolerance
• Controlled insertion force (per connector specification) applied by a calibrated press tool to ensure full pin engagement without damaging the PCB hole or the compliant pin zone
• Post-insertion inspection to verify pin protrusion on the opposite side of the board (confirming full insertion) and absence of PCB damage around the hole annular ring

---

Step 18: Functional Test and Burn-In

The fully assembled GPU PCB undergoes functional testing before delivery:

• Power-on test: Verifies that all power rails come up to correct voltage and within specified sequence; checks for shorts (overcurrent) and open circuits (missing rails) before applying full power to GPU packages
• GPU enumeration test: The board is connected to a test host system; correct GPU enumeration (all GPUs detected by the PCIe host) and NVLink topology detection (all NVSwitch connections recognized) verifies that all BGA solder joints are functional at the system level
• Throughput test: GPU compute benchmarks and memory bandwidth tests verify that all GPU dies, HBM stacks, and interconnects are functional and meeting specification
• Burn-in: Extended operation at elevated temperature (typically 55–70°C ambient) and high GPU utilization for 24–72 hours; screens for infant mortality failures (latent defects in solder joints or via plating that manifest early in operation) before the board reaches the end customer
• Thermal imaging: Infrared camera imaging during burn-in identifies hot spots that indicate high-resistance connections, missing thermal interface material, or thermal management failures

---

Quality Standards for GPU PCBs

Standard	Scope	Relevance to GPU PCBs
IPC-6012 Class 3	Qualification and performance of rigid PCBs	Mandatory for AI server boards; defines minimum copper thickness, annular ring, hole quality, and registration requirements
IPC-A-600 Class 3	Acceptability of printed boards (visual inspection)	Acceptance criteria for surface defects, laminate voids, and solder mask quality
IPC-A-610 Class 3	Acceptability of electronic assemblies	Solder joint acceptance criteria for BGA, SMT, and through-hole components on GPU PCBA
IPC-7095	Design and assembly process implementation for BGA	BGA void acceptance criteria, X-ray inspection requirements, rework guidelines for GPU and NVSwitch packages
ISO 9001	Quality management systems	Required for fabricators and assemblers supplying AI server hardware programs
IPC-TM-650 2.5.5.7	Controlled impedance test method	TDR test procedure for verifying impedance of NVLink and PCIe signal coupon structures
JEDEC JESD22	Reliability test methods for microelectronics	Thermal cycling, thermal shock, and moisture sensitivity testing for BGA assemblies on GPU boards

---

FAQ

How long does it take to manufacture a GPU PCB from bare board to PCBA?
Lead time depends heavily on complexity. A 16-layer H100 baseboard prototype with HDI and backdrilling typically takes 15–20 business days for bare board fabrication, plus 5–10 business days for SMT assembly and test. A 32-layer B200 baseboard with 3+N+3 HDI, any-layer microvias, copper coin inserts, and backdrilling may require 25–35 business days for fabrication alone. Total prototype-to-delivered-PCBA lead time is typically 4–8 weeks for high-complexity AI server boards.

What is the most common failure mode in GPU BGA assembly?
The most common GPU BGA failure modes are: solder voids (gas entrapment in the solder joint, caused by flux outgassing or contamination on the pad surface); solder bridges (adjacent balls shorting, more common at fine pitch); and head-on-pillow (HoP) defects (the solder paste and the BGA ball do not fully coalesce, creating a mechanically weak joint that passes visual and even X-ray inspection but fails in thermal cycling). HoP is mitigated by optimized reflow profile, nitrogen atmosphere, and nitrogen-compatible flux chemistry.

Why do GPU PCBs require controlled-depth backdrilling?
Through-hole via stubs act as transmission line stubs that resonate at specific frequencies, creating notches in the signal frequency response. At NVLink 4.0 speeds (100 Gb/s per lane), these notches fall within the signal bandwidth and degrade bit error rate. Backdrilling removes the stub by drilling from the opposite board face to a controlled depth, eliminating the resonance. For NVLink 5.0 at 200 Gb/s per lane, the stub resonance frequency requirement is twice as stringent, requiring even shorter residual stubs after backdrilling (< 5 mils). See What Is NVLink? for signal integrity context.

Can a GPU PCB be reworked if a BGA fails?
Yes, BGA rework is possible but technically challenging on GPU and NVSwitch packages. The package must be heated uniformly to reflow temperature using a hot air or IR rework station with a custom nozzle sized to the package footprint, without overheating adjacent components or the PCB laminate. After removal, the pad array must be cleaned, inspected, and reprinted with solder paste before a new package is placed. Large BGA packages (40–60 mm) have high thermal mass and require precise rework station programming. Rework yield is lower than initial assembly yield, and reworked boards should undergo full X-ray and functional verification before release.

What is via-in-pad and why is it used on GPU PCBs?
Via-in-pad (VIPPO—Via-In-Pad Plated Over) places a via directly within a BGA or SMT pad rather than adjacent to it. This allows signal escape routing directly beneath a fine-pitch BGA package, where conventional pad-adjacent vias would not fit within the pad pitch. On GPU PCBs with SXM5 or SXM6 sockets having very high pin counts and fine pitch, via-in-pad is necessary to achieve the routing density required in the innermost rows of the BGA array. The via must be filled with epoxy and cap-plated to present a flat, solderable surface; an open via in a BGA pad would create a solder void during reflow as solder paste flows into the via hole.

What quality class should GPU PCBs be manufactured to?
IPC Class 3 (High Reliability) is the appropriate quality class for AI server GPU PCBs. Class 3 specifies the most stringent requirements for copper thickness in via barrels, annular ring minimum dimensions, hole quality, and surface finish coverage. Class 2 (Standard Reliability) is insufficient for the sustained high-power operation, thermal cycling severity, and long service life expected of data center AI server boards. For AI training systems running continuously for months, IPC Class 3 fabrication combined with extended burn-in testing is the minimum responsible specification.

---

Need to Manufacture AI Server PCBs?

From inner layer fabrication through final functional test, GPU PCB manufacturing demands process capabilities and quality systems that go well beyond standard commercial board production. NextPCB supports the complete manufacturing sequence for AI accelerator hardware—high-layer-count fabrication, sequential HDI lamination, controlled-depth backdrilling, via-in-pad processing, low-loss laminate handling, BGA assembly, 3D X-ray inspection, and burn-in test services.

 

---

Related Articles:

• AI Accelerator PCB Design Guide: Layers, Materials and Signal Integrity for H100/H200 Boards
• What Is an AI Server? Architecture, Components & PCB Requirements
• A100 vs H100: GPU Generational Leap & PCB Stack Differences Explained
• NVIDIA Blackwell Architecture Explained: B200, GB200 & PCB Design Impact
• What Is NVLink? How NVIDIA's High-Speed GPU Interconnect Shapes PCB Routing
• AI Training vs AI Inference: Why They Need Different PCB Designs
• What Is an OAM Module? Open Accelerator Module Standard for AI Hardware