Decoupling Capacitor Placement: Rules & Strategies for High-Speed PCB

Introduction

Decoupling capacitors are the most common component on any digital PCB, yet they are also among the most frequently misapplied. Engineers place them too far from the IC, use the wrong dielectric type, connect them through excessively long traces, or select values based on rules of thumb that ignore the actual impedance the power delivery network must achieve. The result is a power rail that looks clean on a schematic but delivers noisy, transient-laden voltage to every logic transition in the design.

In high-speed PCB design—FPGAs, CPUs, DDR5 memory interfaces, SerDes transceivers, and AI accelerator power delivery networks—decoupling is not a checkbox at the end of layout. It is a first-order design constraint that determines whether the design meets timing specifications, emissions limits, and signal integrity requirements. This guide covers the theory, strategy, and practical placement rules for decoupling capacitors at every tier of the power delivery hierarchy.

1. Table of Contents

• Introduction
• Why Decoupling Capacitors Are Necessary
• The Three-Tier Decoupling Strategy
• Capacitor Value Selection
• Dielectric Selection: C0G vs X7R for Decoupling
• Placement Distance: How Close Is Close Enough?
• Via Placement Strategy
• Power Plane and PDN Interaction
• Parallel Capacitors: Why More Is Better
• High-Density Decoupling: 0201 Arrays and Via-in-Pad
• 12 Practical Placement Rules
• Common Decoupling Mistakes and How to Fix Them
• Simulation and Verification
• FAQ

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Why Decoupling Capacitors Are Necessary

Every digital switching event in a logic device causes a current transient on the power supply. When a CMOS gate switches from low to high, it briefly connects the supply rail to the output through a PMOS transistor, drawing a current spike. When it switches from high to low, it discharges the output node through an NMOS transistor, injecting current back toward the ground rail. In a modern microprocessor with hundreds of millions of switching events per clock cycle, these transients sum to a continuously fluctuating current demand that the power supply cannot respond to instantaneously.

The power supply regulation loop has a response time measured in microseconds to milliseconds—far too slow to respond to current transients measured in nanoseconds. Without local charge storage, the supply voltage at the IC's power pins droops during high-current switching events and overshoots during low-current periods. This voltage noise:

• Reduces the noise margin of internal logic, increasing the probability of metastability and timing errors
• Couples through the substrate and interconnects, appearing as jitter on clock signals and as data-dependent noise on high-speed differential pairs
• Radiates from the PCB as electromagnetic interference (EMI), which may fail regulatory emissions tests
• Creates ground bounce that shifts the reference level of digital logic outputs

Decoupling capacitors solve this problem by providing a local charge reservoir adjacent to the IC. When the IC demands a current transient, the decoupling capacitors supply the charge immediately from their stored energy, maintaining a stable voltage at the power pins. The power supply then has time to recharge the capacitors during lower-demand periods.

The key insight is that the effectiveness of decoupling is determined not by the capacitance value alone, but by the impedance of the path from the capacitor to the IC power pin at the frequency of the transient. Low impedance at high frequency requires small capacitors close to the IC, not large capacitors far away.

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The Three-Tier Decoupling Strategy

Effective power delivery network (PDN) decoupling uses three tiers of capacitance, each targeting a different frequency range of the current transient spectrum:

Tier 1 — Bulk Capacitance (1–100 μF, 10 Hz – 1 MHz): Large electrolytic or polymer capacitors located near the voltage regulator output. These handle slow, large-amplitude current variations such as the difference between standby and active operating states, power-up inrush, and load steps on millisecond timescales. They are typically 10–100 μF aluminum electrolytic or solid polymer capacitors placed near the regulator output and at each major load area. While MLCCs are now available in 100 μF values, bulk electrolytic or polymer capacitors offer better cost-to-capacitance ratio at this tier and don't suffer from the severe DC bias derating that affects large-value Class II MLCCs.

Tier 2 — Mid-Frequency Decoupling (100 nF – 10 μF, 1 MHz – 100 MHz): X7R or X5R MLCCs in 0402 or 0603 packages, placed within 2–5 mm of each IC. These handle the intermediate-frequency transients from I/O switching, clock distribution, and moderate-speed logic transitions. The most common specification is 100 nF X7R in 0402 package—one per power pin on dense ICs, or one per power supply domain on less demanding components. For the dielectric selection reasoning at this tier, see the discussion at What Is an MLCC?

Tier 3 — High-Frequency Decoupling (1–100 nF, 100 MHz – 1 GHz+): C0G/NP0 or low-ESL X7R MLCCs in 0201 or 0402 packages, placed immediately adjacent to or under the IC power pins. These handle the fastest transients from SerDes transmitters, DDR5 data switching, and RF circuits. At these frequencies, ESL dominates over capacitance value: a 1 nF capacitor with 0.3 nH ESL provides a lower impedance at 500 MHz than a 100 nF capacitor with 1.5 nH ESL. Package size (0201 < 0402 < 0603) is the primary knob for reducing ESL at this tier.

Tier	Capacitance Range	Frequency Target	Component Type	Package	Placement Distance from IC
1 (Bulk)	10–100 μF	10 Hz – 1 MHz	Electrolytic / polymer / large MLCC	Radial / SMD polymer / 1206–1210	10–50 mm
2 (Mid-frequency)	100 nF – 10 μF	1–100 MHz	X7R / X5R MLCC	0402 / 0603	1–5 mm
3 (High-frequency)	1–100 nF	100 MHz – 1 GHz+	C0G or low-ESL X7R	0201 / 0402	< 1 mm (ideally < 0.5 mm)

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Capacitor Value Selection

The correct capacitor value for a given application depends on the target impedance of the PDN, the frequency content of the transient current, and the IC's di/dt specification. In practice, most engineers start with the IC manufacturer's recommended decoupling from the datasheet and refine through simulation or measurement.

A simplified starting point for common ICs:

Component Type	Tier 2 Starting Value	Tier 3 Starting Value	Notes
General logic IC (74-series, simple gates)	100 nF per VCC pin	Not typically needed	Single 100 nF per package or per 2 VCC pins is standard
Microcontroller (STM32, nRF52, etc.)	100 nF per VCC/VDDIO pin	10 nF near core power pins	Multiple VCC domains; check datasheet per domain
FPGA (Xilinx, Intel, Lattice)	100 nF per bank VCC + 4.7 μF bulk per bank	10–100 nF C0G near VCCINT	FPGA power integrity guides define per-bank requirements in detail; follow vendor AN
DDR5 memory (DRAM + controller)	100 nF per VDD/VDDQ pin	10 nF C0G near VDD pins	JEDEC specification requires tight VDD/VDDQ decoupling; refer to memory vendor layout guidelines
High-speed SerDes (PCIe, USB3, Ethernet)	100 nF per AVDD/DVDD pin	10 nF C0G per analog supply pin	Separate analog and digital decoupling; ferrite bead isolation between analog and digital supply domains
GPU / AI accelerator core (VCORE)	100 nF per power delivery pin (0201)	1 nF C0G immediately under package (0201 via-in-pad)	Thousands of capacitors in array; PDN simulation required; target Z < 0.1 mΩ

The self-resonant frequency (SRF) of the capacitor must be considered when selecting values. A 100 nF MLCC in 0402 package has an SRF of approximately 50–80 MHz; above this frequency, it behaves as an inductor and provides no useful decoupling. If decoupling is needed at 200 MHz, a 10 nF or 1 nF capacitor in a smaller package with SRF above 200 MHz must be used. The general guideline is that the target frequency must be below the SRF by at least a factor of 3× for effective decoupling.

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Dielectric Selection: C0G vs X7R for Decoupling

Most power supply decoupling uses X7R dielectric (or X5R for maximum capacitance density). X7R provides the capacitance density needed for practical decoupling values in small packages. However, C0G/NP0 should be used in specific situations:

• PLL and clock supply bypass: X7R capacitors generate microphonic (piezoelectric) noise when the PCB vibrates or when AC voltage is applied across them. On a PLL supply, this noise can corrupt the VCO control voltage and increase phase noise / clock jitter. C0G capacitors have no piezoelectric effect and are the correct choice for PLL AVDD/VCO supply decoupling
• ADC reference supply: The capacitance stability of C0G prevents the reference voltage filter frequency from drifting with temperature, maintaining consistent ADC linearity
• High-frequency RF supply: C0G provides lower loss (higher Q) at RF frequencies, making it more effective for RF IC supply bypass at GHz frequencies
• Any supply where the X7R piezoelectric noise floor is a concern: Linear regulators driving precision analog circuits should use C0G output bypass capacitors to avoid feeding piezoelectric noise into the downstream circuitry

For general digital logic decoupling (processor cores, FPGA fabric, DDR interfaces, most I/O), X7R in 0402 or 0201 provides the best capacitance-to-size ratio at acceptable cost. Remember to account for X7R DC bias derating: a 100 nF / 10 V X7R capacitor on a 3.3 V rail delivers closer to 75–85 nF at operating voltage—always use a voltage rating of at least 2× the rail voltage to keep capacitance near nominal.

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Placement Distance: How Close Is Close Enough?

The most critical placement rule for decoupling capacitors is distance from the IC power pin. Every millimeter of PCB trace between the capacitor and the IC power pin adds inductance that raises the impedance of the decoupling path at high frequencies.

A practical estimate: a PCB trace 0.1 mm wide adds approximately 0.7–1.0 nH of inductance per millimeter of length. The inductive reactance at frequency f is X_L = 2πfL. At 100 MHz, 1 nH of trace inductance adds 0.63 Ω in series with the decoupling capacitor—which negates the benefit of the low-ESL 0201 MLCC you carefully selected.

Trace Length from Cap to IC Pin	Added Trace Inductance (est.)	Impedance Added at 100 MHz	Impedance Added at 500 MHz
0 mm (via-in-pad)	~0 nH (via only: ~0.3 nH)	~0.2 Ω	~0.9 Ω
0.5 mm	~0.4–0.5 nH	~0.3–0.5 Ω	~1.3–1.6 Ω
1 mm	~0.7–1.0 nH	~0.4–0.6 Ω	~2.2–3.1 Ω
3 mm	~2.1–3.0 nH	~1.3–1.9 Ω	~6.6–9.4 Ω
10 mm	~7–10 nH	~4.4–6.3 Ω	~22–31 Ω

The practical distance limits are:

• High-frequency (Tier 3) capacitors: < 0.5 mm from the power pin; ideally via-in-pad directly beneath the IC package on the opposite board side
• Mid-frequency (Tier 2) capacitors: < 3–5 mm from the IC power pin; same side of the board as the IC
• Bulk (Tier 1) capacitors: Within 20–50 mm of the power supply output or load center; the bulk capacitance is less location-sensitive because low-frequency impedance is dominated by the capacitance value, not the trace inductance

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Via Placement Strategy

The via that connects the decoupling capacitor to the power plane and the IC power pin is often the dominant inductance in the decoupling loop—not the trace between the capacitor and the IC. A standard 0.3 mm diameter through-hole via contributes approximately 0.3–0.5 nH of inductance. If there are two vias in the loop (one on each capacitor pad), the total via inductance is 0.6–1.0 nH before any trace inductance is added.

Best practices for via placement in decoupling circuits:

• Place vias as close to the capacitor pads as possible: The via should be adjacent to the capacitor pad, connected by the shortest possible trace or direct pad-to-via connection. Many PCB designers use a “dog-bone” via pattern where the via is directly adjacent to the capacitor pad with no intermediate trace at all
• Use two vias per capacitor when space allows: Placing one via at each end of the capacitor (one on the power side, one on the ground side) creates two parallel current paths, approximately halving the effective via inductance
• Use via-in-pad (VIPPO) for the highest-frequency applications: Placing the via directly within the capacitor pad eliminates the trace-to-via segment entirely. The via delivers charge directly from the power plane to the pad. Via-in-pad requires the via to be filled with conductive epoxy and cap-plated to create a flat, solderable surface. This is standard practice in high-density AI server baseboard designs where 0201 MLCCs are placed under BGA packages
• Do not share vias between multiple capacitors: Each capacitor should have its own dedicated vias; sharing vias between capacitors creates mutual inductance that degrades both capacitors' high-frequency effectiveness
• Connect both power and ground vias to planes, not traces: The capacitor's power via should connect directly to a solid power plane, and the ground via should connect directly to a solid ground plane. Connecting through traces to a remote via adds inductance in series with both terminals of the capacitor

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Power Plane and PDN Interaction

Power and ground planes are themselves a form of distributed capacitance. Two closely spaced parallel copper planes separated by a thin dielectric form a parallel plate capacitor with capacitance C = ε_r × ε₀ × A / d. For a typical 100 mm × 100 mm power/ground plane pair separated by 100 μm of FR4 (Dk ~4.5):

C = 4.5 × 8.85 × 10⁻¹² F/m × 0.01 m² / 0.0001 m ≈ 4.0 nF

This distributed capacitance provides very low-inductance decoupling at very high frequencies (above the SRF of individual discrete capacitors) because the current path through the planes is uniformly distributed across the entire area with essentially zero series inductance. However, 4 nF is far too small to handle the bulk of transient decoupling requirements; discrete capacitors are still necessary for mid-frequency decoupling.

The interaction between discrete decoupling capacitors and power planes matters for two reasons:

1. Anti-resonance peaks: When two different capacitance tiers are combined on the same power rail, the impedance versus frequency curve can exhibit anti-resonance peaks where the impedance rises above the target level. This typically occurs at the frequency where the inductance of the bulk capacitors (now acting as inductors above their SRF) resonates with the capacitance of the mid-frequency capacitors. Careful value selection and spacing across the PDN can suppress or move these peaks outside the target frequency band
2. Plane splits: Any gap or split in the power or ground plane breaks the distributed capacitance and creates an inductance boundary. High-frequency decoupling capacitors should never be placed such that the current loop crosses a plane split; the inductance of the split will degrade the decoupling effectiveness by an order of magnitude or more at high frequencies

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Parallel Capacitors: Why More Is Better

Placing multiple decoupling capacitors in parallel does more than simply add their capacitances. Parallel capacitors also reduce the effective ESL of the decoupling network, because inductances in parallel combine as L_eff = L / n (where n is the number of identical capacitors in parallel with mutual inductance close to zero). Four 100 nF capacitors in parallel have approximately four times the capacitance and one-quarter the ESL of a single 100 nF capacitor, raising the SRF by approximately 2× and reducing the impedance at high frequencies by approximately 6 dB.

This is why GPU power delivery networks use thousands of small capacitors rather than a smaller number of large ones: spreading 0201 MLCCs in dense arrays around the GPU package creates a very low-impedance, low-inductance decoupling network that can sustain GPU VCORE at spec during the rapid current transients of AI compute workloads.

When using parallel capacitors, it is counterproductive to use very different values in parallel (for example, a 100 μF and a 100 nF directly in parallel without any separation). The combination can create a strong anti-resonance peak between the two capacitors' self-resonant frequencies. Best practice is to use capacitors within one decade of each other at each tier, or to include a small series resistance or ferrite bead between tiers to damp the anti-resonance.

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High-Density Decoupling: 0201 Arrays and Via-in-Pad

For high-speed processors, FPGAs, and AI accelerators, the decoupling network becomes a major PCB design challenge in its own right. A modern FPGA like a Xilinx UltraScale+ or Intel Stratix 10 may require 200–500 decoupling capacitors across dozens of power supply domains. A GPU baseboard for AI training requires tens of thousands of MLCCs.

The design strategies for high-density decoupling:

• Place capacitors on the back side of the board directly under the BGA: For BGA-packaged ICs, placing decoupling capacitors on the opposite side of the PCB directly beneath the package—connected to the power delivery vias that pass through the board—achieves the shortest possible current path. This requires via-in-pad on the power delivery vias or very short traces from the via exit to the capacitor pad on the back side
• Use 0201 packages for the innermost capacitors: 0201 (0.6 mm × 0.3 mm) packages can be placed at 0.8–1.0 mm pitch, enabling very high placement density around or under BGA packages. They have approximately 40% lower ESL than equivalent 0402 capacitors, providing better high-frequency performance where it matters most
• Grid arrays of identical capacitors: Placing a uniform grid of same-value capacitors (for example, a 10 × 10 array of 100 nF 0201 capacitors under a large FPGA) provides a uniform, predictable PDN impedance that is easier to simulate and verify than asymmetric layouts
• Dedicated PDN simulation: For AI server boards and high-performance FPGAs, PDN simulation using tools like Ansys SIwave or Cadence Sigrity is necessary to verify that the target impedance (< 1 mΩ for CPU cores; < 0.1 mΩ for GPU VCORE) is achieved across the relevant frequency band. The simulation guides capacitor count, value distribution, and via placement optimization

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12 Practical Placement Rules

1. 1. Place mid-frequency decoupling capacitors within 3 mm of the IC power pin they serve. Beyond this distance, trace inductance significantly degrades high-frequency effectiveness.
2. Place high-frequency (Tier 3) capacitors within 0.5 mm or use via-in-pad. At 500 MHz and above, 1 mm of trace inductance exceeds the SRF-limited impedance of the capacitor itself.
3. Connect the capacitor power via directly to a solid power plane, not through a trace segment. Any trace between the via and the plane adds inductance in the current return path.
4. Use two vias per capacitor where space permits. The via to the power plane on one pad, the via to the ground plane on the other pad, as close to the pads as possible.
5. Do not route signal traces between the decoupling capacitor and the IC power pin. The current loop formed by a decoupling capacitor and its IC must be as small and direct as possible.
6. Orient the capacitor long axis parallel to the current flow direction. This minimizes the trace inductance of the pad-to-trace-to-via segment.
7. Place decoupling capacitors on the same board side as the IC when possible. Back-side placement directly under the IC is the best option for BGA decoupling; a capacitor on the opposite side of the board with vias is preferable to a same-side capacitor placed 5 mm away.
8. Do not place decoupling capacitors across plane splits. The current loop must not cross any break in the reference plane.
9. Separate PLL and clock supply decoupling from general decoupling. Use C0G/NP0 for PLL AVDD and isolate from the main digital supply with a ferrite bead or small inductor.
10. Match via size to capacitor package size. A 0201 capacitor connected to a 0.3 mm via is limited by the via inductance; consider 0.2 mm laser-drilled microvias for the highest-density 0201 decoupling arrays.
11. Apply voltage derating when selecting X7R values. Use capacitors rated at 2×–3× the supply voltage to ensure adequate actual capacitance under DC bias. A 100 nF / 10 V capacitor on a 3.3 V rail delivers closer to 90 nF; a 100 nF / 4 V capacitor on the same rail may deliver only 50–60 nF.
12. Simulate the PDN impedance before sign-off on high-performance designs. Spreadsheet calculations can identify gross problems, but accurate PDN simulation using the actual layout geometry is necessary to guarantee target impedance compliance for FPGA, CPU, and AI accelerator designs.

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Common Decoupling Mistakes and How to Fix Them

Mistake	Why It Is a Problem	Fix
Placing all decoupling caps far from the IC (5–20 mm away)	Trace inductance negates the capacitor's high-frequency effectiveness; supply impedance is dominated by trace L, not C	Move Tier 2 caps within 3 mm; add Tier 3 caps via-in-pad or within 0.5 mm under the package
Using only one large 10 μF capacitor per IC instead of multiple small caps	Large capacitor has high ESL; SRF below the frequency of fast transients; poor high-frequency decoupling	Replace with tiered strategy: multiple 100 nF in 0402 + smaller 10 nF or 1 nF in 0201
Routing signal traces between the decoupling cap and the IC power pin	Creates a larger current loop area, increases inductance and radiated emissions	Keep the capacitor-to-IC current path free of any signal routing; use a keepout zone
Connecting decoupling cap to the IC via a thin, long trace	Thin traces (e.g., 0.05 mm) have even higher inductance per mm than standard traces	Use the widest trace the land pattern allows; minimize trace length; use direct via-to-pad connections
Using Y5V dielectric for supply decoupling	Y5V loses up to 80% capacitance at operating voltage and temperature; actual delivered capacitance is a fraction of nominal	Replace with X7R (same package size, same capacitance value) at appropriate voltage rating
Using X7R on PLL / clock supply without C0G isolation	X7R piezoelectric noise corrupts PLL VCO voltage; increases phase noise and clock jitter	Use C0G on PLL supply bypass; add ferrite bead between main VCC and PLL AVDD
Sharing vias between multiple capacitors	Creates mutual inductance between the capacitor current loops; degrades effectiveness of all connected caps	Give each capacitor its own dedicated power and ground vias
Not accounting for DC bias derating on X7R caps	Actual delivered capacitance 30–70% below nominal; PDN impedance target not met	Use voltage rating 2×–3× the supply voltage; verify actual C using manufacturer simulation tools

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Simulation and Verification

For simple designs (microcontrollers, basic digital boards), following the rules above and the IC manufacturer's recommended decoupling from the datasheet is sufficient. For high-performance designs—FPGAs, CPUs, DDR5 interfaces, AI accelerator boards—PDN simulation is necessary to verify target impedance compliance before PCB layout is complete.

The PDN simulation workflow:

1. Define the target impedance Z_target = ΔV / ΔI, where ΔV is the maximum allowable voltage ripple (typically 5% of supply voltage) and ΔI is the maximum current transient. For a 1 V core supply with 5% ripple and 10 A transient: Z_target = 0.05 V / 10 A = 5 mΩ
2. Model the VRM as a lumped circuit with its output impedance and bandwidth
3. Add bulk capacitance models (including ESR and ESL from component datasheets)
4. Import the PCB power/ground plane geometry into an electromagnetic solver (Ansys SIwave, Cadence Sigrity, or CST)
5. Place discrete decoupling capacitor models at their actual layout locations
6. Plot PDN impedance vs frequency from the IC power pin perspective; verify that impedance stays below Z_target across the target frequency band
7. Iterate capacitor values, counts, and placement until the impedance target is met at all frequencies

Many IC manufacturers (Intel, AMD, Xilinx/AMD, Microchip) provide PDN design guides and reference simulation models specific to their devices. These should be the starting point for PDN simulation of high-performance ICs rather than generic approaches.

For designs that require high-density HDI PCB technology to accommodate 0201 via-in-pad decoupling arrays, NextPCB's HDI PCB capabilities support sequential build-up, laser-drilled microvias, and via-in-pad with copper fill to achieve the tightest possible decoupling placement geometry.

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FAQ

What is the difference between a decoupling capacitor and a bypass capacitor?
The terms are often used interchangeably, but there is a subtle distinction. A bypass capacitor provides a low-impedance path to ground for AC noise on a supply rail—it “bypasses” high-frequency noise around the load. A decoupling capacitor isolates one circuit from another through the power supply—it “decouples” the transient current demands of one IC from disturbing the supply voltage seen by another IC. In practice, the same physical capacitor performs both functions: it bypasses AC noise on the rail and decouples the transient demand of its associated IC. Most engineers use the terms interchangeably, and the same component is recommended whether you call it a bypass or a decoupling capacitor.

How many decoupling capacitors does a typical IC need?
It depends on the IC's power pin count, current consumption, and switching speed. A simple microcontroller with one VCC pin typically needs one 100 nF capacitor plus one 10 μF bulk capacitor nearby. A complex FPGA with dozens of separate power domains (VCCINT, VCCO_0 through VCCO_7, VCCAUX, MGT supply, etc.) may require 200–500 capacitors total. Modern AI accelerator GPUs with thousands of power delivery pins and PDN impedance targets below 1 mΩ require tens of thousands of capacitors. Always start with the IC manufacturer's power supply recommendation in the datasheet and adjust based on PDN simulation results.

Can I place decoupling capacitors on the opposite side of the board from the IC?
Yes, and for BGA-packaged ICs it is often the best placement option. A 0201 capacitor placed directly beneath the BGA footprint on the opposite board side, connected via the BGA power delivery vias, achieves a shorter current path than a capacitor placed 3–5 mm away on the same side. The via connection introduces approximately 0.3–0.5 nH per via, but this is less than the trace inductance of a same-side capacitor at any significant distance. Via-in-pad on the back-side capacitor eliminates even the pad-to-via trace segment.

Does the capacitor value matter more than its placement?
Placement matters more than value for high-frequency decoupling. A 100 nF capacitor placed 0.5 mm from the IC power pin outperforms a 1 μF capacitor placed 10 mm away at frequencies above 10–20 MHz, because the 10 mm trace inductance raises the 1 μF capacitor's effective impedance well above that of the closer 100 nF capacitor. Value selection matters for ensuring adequate capacitance at low frequencies and adequate SRF at high frequencies, but these are secondary to getting the capacitor physically close to the load it is decoupling.

What is target PDN impedance and how do I calculate it?
Target PDN impedance (Z_target) is the maximum power delivery network impedance that keeps supply voltage ripple within specification. It is calculated as Z_target = ΔV / ΔI, where ΔV is the maximum tolerable voltage ripple (typically 5% of supply voltage) and ΔI is the maximum expected current transient. For a 1.0 V core supply at 5% ripple with a 20 A transient: Z_target = 0.05 / 20 = 2.5 mΩ. The PDN impedance (measured from the IC power pin) must stay below this value at all frequencies from DC to the highest-frequency current transient the IC produces. Modern processors and GPUs may require Z_target as low as 0.1–0.5 mΩ, which demands sophisticated decoupling network design and simulation.

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Need PCB Manufacturing and Assembly for Your High-Speed Design?

Correct decoupling capacitor placement is only realized in production if the PCB manufacturing process delivers the tight tolerances and assembly precision the design requires—whether that means 0201 MLCC placement in dense arrays, via-in-pad for under-BGA decoupling, or HDI board construction for high-layer-count AI server designs.

NextPCB provides complete PCB fabrication and assembly services including high-density SMT assembly, HDI PCB with via-in-pad, and automated optical and X-ray inspection. Upload your Gerber files to the online Gerber viewer for a free DFM check, or go straight to a quote.