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Signal Integrity Research: Emphasis on Signal Rise Time
Posted:02:38 PM November 26, 2018 writer: G

The signal rise time is not the time it takes for the signal to go from low to high, but part of it. The definition of the industry has not been unified, the best way is to follow the definition of upstream chip manufacturers, after all, these giants have the right to speak. There are usually two types: the first is defined as a 10-90 rise time, which is the time it takes for the signal to rise from 10% of the high level to 90%. The other is the 20-80 rise time, which is the time it takes for the signal to rise from 20% of the high level to 80%. Both are used, as can be seen from the IBIS model. For the same waveform, the natural 20-80 rise time is shorter.

Ok, just knowing this is enough. For our terminal applications, accurate numbers are sometimes not very important, and this digital chip manufacturer usually does not directly list them. Of course, some chips can roughly estimate this value from the IBIS model, unfortunately, not every You can find the IBIS model for all kinds of chips.

The important thing is that we must establish the concept that rise time has a significant impact on circuit performance, as long as it is as small as a certain range, it must be noticed, even if it is a very vague range. There is no need to define this range standard precisely, nor is it practical. Just remember that the current chip processing process makes this time very short, it has reached the ps level, and you should pay attention to his influence.

As the rise time of the signal decreases, problems such as reflection, crosstalk, track collapse, electromagnetic radiation, and ground bounce become more serious, and the noise problem is more difficult to solve. The design of the previous generation may not be applicable in this generation.

The decrease in signal rise time is equivalent to an increase in signal bandwidth from the perspective of spectrum analysis, that is, there are more high-frequency components in the signal, and it is these high-frequency components that make design difficult. Interconnect lines must be treated as transmission lines, creating many problems that were not previously available.

Therefore, to learn signal integrity, you must have the concept that the steep rising edge of the signal is the culprit in generating signal integrity problems.

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