This paper mainly uses Cadence's time domain analysis tool to quantify the DDR3 design, introduces the main factors affecting signal integrity, analyzes the timing of DDR3, improves and optimizes the design by analyzing the results, improving signal quality and reliability. Security has been greatly improved.
1. Introduction to DDR3
DDR3 memory is similar to DDR2 memory in that it contains two parts of the controller and the memory, all of which use source synchronous timing, that is, the strobe signal (clock) is not sent by an independent clock source, but is sent by the driver chip. It has a higher data transfer rate than DR2, up to 1866Mbps; DDR3 also uses 8-bit prefetch technology to significantly increase the storage bandwidth; its operating voltage is 1.5V, which guarantees lower power consumption at the same frequency.
The DDR3 interface design is difficult to implement. It adopts the unique Fly-by topology and uses "Write leveling" technology to control the internal offset timing of the device. Although it plays a role in ensuring design implementation and signal integrity, it is not comprehensive to realize high-frequency and high-bandwidth storage systems. Simulation analysis is required to ensure design implementation and signal quality integrity.
2. Simulation analysis
The simulation analysis of DDR3 is based on the combination of the project: PowerPC 64-bit dual-core CPU module is selected, which uses Micron's MT41J256M16HA-125IT as the memory. Freescale P5020 analyzes the processor. The module configuration memory bus data transmission rate is 1333MT/s, and the simulation frequency is 666MHz.
3. Preparation before simulation
Before the analysis, it is necessary to communicate with the printed board manufacturer according to the impedance of DDR3 to confirm the laminated structure of the PCB. The key to ensuring good transmission line performance in high-speed transmission is continuous characteristic impedance. It is determined that the impedance of the high-speed PCB signal line is controlled within a certain range, making the printed board a "controllable impedance plate", which is the basis of simulation analysis. The DDR3 bus has a single-wire impedance of 50Ω and a differential line impedance of 100Ω.
Set the voltage value of the analysis network terminal; include the passive device assignment model for the analyzed device; determine the device class attribute; ensure the device pin attributes (input\output, power\ground, etc.)
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