In order to develop a unified IBIS format, EDA companies, IC suppliers and end users set up an IBIS format development committee, and the IBIS Open Forum was born. It is composed of some EDA vendors, computer manufacturers, semiconductor manufacturers and universities.
In 1993, the format development committee introduced the first standard of IBIS, Version 1.0, which was revised continuously. The latest official version is Version 4.1 published in 2004. V4.1 mainly incorporates multi-language models. Support, including Berkeley SPICE, VHDL-AMS and Verilog-AMS, the IBIS model has the ability to model the entire system, the scope of the model application has been greatly expanded, but this requires a hybrid simulation engine that supports these models at the same time. Simulation, so the large-scale application of the model's software will take time. The IBIS standard has been approved by the EIA and is defined as the ANSI/EIA-656-A standard. Each new version adds some new content, but these new content are just optional items in an IBIS model file rather than mandatory items, which guarantees backward compatibility of the IBIS model.
Now, dozens of EDA companies have become members of the IBIS Open Forum, supporting EBI companies of IBIS to provide IBIS models and software simulation tools for different devices. More and more semiconductor manufacturers are beginning to offer their own IBIS models. Since the IBIS model does not need to describe the internal design of the I/O unit and the transistor manufacturing parameters, it has been welcomed and supported by semiconductor manufacturers. Now major digital IC manufacturers are able to provide the corresponding IBIS models while providing chips.
The IBIS specification itself is just a file format that describes how to record the different parameters of a chip's driver and receiver in a standard IBIS file, but does not explain how these recorded parameters are used. These parameters need to be used by the IBIS model. The simulation tool to read.
The IBIS model only provides a description of the behavior of the driver and receiver, but does not reveal the intellectual property details of the internal construction of the circuit. In other words, vendors can use the IBIS model to illustrate their latest door-level design work without revealing too much product information to their competitors. Moreover, because IBIS is a simple model, the PCB level simulation is performed by look-up table calculation, so the calculation amount is small, and the calculation amount is 10 to 15 times less than the corresponding full Spice triode model simulation.
IBIS provides two complete I/V curves that represent the drive's high and low states, as well as the state transitions at a determined slew rate. The role of the I/V curve is to provide IBIS with the ability to model nonlinear effects such as protection diodes, TTL totem pole drive sources, and emitter follower outputs. The accuracy of the analysis of the IBIS model depends mainly on the number of data points and the accuracy of the data in the I/V and V/T tables.
Compared with the Spice model, the advantages of the IBIS model can be summarized as:
Provides accurate models in terms of I/O nonlinearity, taking into account the parasitic parameters of the package and the ESD structure;
Provide faster simulation speeds than structured methods;
Can be used for system board level or multi-board signal integrity analysis simulation. Signal integrity issues that can be analyzed with the IBIS model include: crosstalk, reflection, oscillation, overshoot, undershoot, mismatched impedance, transmission line analysis, topology analysis. IBIS is especially capable of accurate and detailed simulation of high-speed oscillations and crosstalk. It can be used to detect signal behavior under worst-case rise time conditions and some situations that cannot be solved by physical tests;
The model can be obtained free of charge from the semiconductor manufacturer, and the user does not need to pay extra for the model;
Compatible with a wide range of simulation platforms in the industry, almost all signal integrity analysis tools accept IBIS models.
Of course, IBIS is not perfect, it also has the following disadvantages:
Many chip vendors lack support for the IBIS model.
Without the IBIS model, the IBIS tool will not work. Although IBIS files can be created manually or automatically converted by the Spice model, any conversion tool can't do anything if you can't get the minimum rise time parameter from the factory.
IBIS does not ideally handle circuits with rise-controlled drive types, especially those that involve complex feedback;
IBIS lacks the ability to model ground bounce noise. The IBIS model version 2.1 contains the mutual inductances that describe the different pin combinations, from which some very useful ground bounce information can be extracted. The reason it doesn't work is the modeling method. When the output transitions from high to low, the large ground bounce voltage can change the behavior of the output driver.
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