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DFM requirements for viewing features in PCB layout design
Posted:05:31 PM August 02, 2018 writer: G

Thermal design requirements for layout

1. The layout takes into account the reasonable smoothness of the heat dissipation channel.

2. The electrolytic capacitor is properly removed from the high heat device.

3. The heating element and the exposed device of the case are not in close proximity to the wire and the thermal element, and other devices should be kept away.

4. Consider the heat dissipation of high power devices and devices under the gusset.

5. Radiator placement Considering the convection problem, there is no high device interference in the projection area of the heat sink, and the surface is marked with silk screen on the mounting surface.


Layout signal integrity requirements

1. Meet the timing requirements for the layout of the synchronous clock bus system.

2. High speed and low speed, digital and analog are arranged separately by module.

3. Determine the topology of the bus based on the analysis of the simulation results or existing experience to ensure that the system requirements are met.

4. The crystal, crystal oscillator, and clock driver chip are placed close to the relevant device.

5. If it is a modified board design, simulate the signal integrity problem reflected in the test report and give a solution.

6. The start match is close to the originating device, and the terminal is matched to the receiving end device.

7. Decoupling capacitors are placed close to the relevant device


EMC requirements

1. The protection circuit is placed near the interface circuit and follows the principle of first protection and filtering.

2. Inductive devices such as inductors, relays, and transformers that are susceptible to magnetic field coupling are not placed close to each other. When there are multiple inductor coils, the direction is vertical and not coupled.

3. Devices with large or very sensitive transmit power (such as crystals, crystals, etc.) are more than 500 mils from the shield and shield case.

4. Place a 0.1uF capacitor near the reset line of the reset switch to reset the device and reset the signal away from other strong interfering devices and signals.

5. The interface device is placed close to the edge of the board. Appropriate EMC protection measures (such as measures with shielded casing and power grounding) have been taken to improve the EMC capability of the design.

6. In order to avoid electromagnetic interference between the soldering surface device and the adjacent single board, the soldering surface of the board is not placed with sensitive components and strong radiation devices.


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