Cost-Driven High-Speed Stackup: 4-Layer & 6-Layer Impedance Control Guide

1. Table of Contents
2. Exploring the Limitations and Optimization Practices of Traditional 4-Layer Stackups
3. Analyzing Impedance Calculation Deviations and Lamination Realities in 6-Layer Boards
4. How to Optimize Manufacturing Costs While Ensuring Signal Quality?
5. Standardized Manufacturing Instructions (Fab Note) Recommendations
6. People Also Ask (Common Engineering Q&A)

In the current hardware design environment, engineers frequently face a dual challenge: on one hand, system interface speeds are continuously increasing (e.g., PCIe 4.0, USB 3.2, and even high-speed DDR memory); on the other hand, due to product life cycles and market competition, BOM cost control has become increasingly stringent. In many projects, routing schemes that could easily be accommodated on an 8-layer board are now required to be implemented on traditional 4-layer or 6-layer through-hole PCBs.

Finding a balance between high-speed signals and a limited number of routing layers requires hardware engineers not only to master the simulation capabilities of EDA software but also to deeply understand the actual lamination processes and material characteristics of PCB factories. This article will explore the common limitations of 4-layer and 6-layer boards in high-speed design and provide impedance control and cost-reduction optimization suggestions based on manufacturing realities.

Exploring the Limitations and Optimization Practices of Traditional 4-Layer Stackups

The most common standard stackup for 4-layer boards is typically Top(Signal) - L2(Power) - L3(Ground) - Bottom(Signal). However, in high-speed digital design, this stackup may have certain limitations in terms of signal integrity (SI) and electromagnetic compatibility (EMC), especially regarding cross-layer routing and return path control.

Challenges Faced by Traditional Stackups

The primary challenge lies in the discontinuity of the return path when high-speed signals transmit across layers.

When a high-speed signal switches from the Top layer to the Bottom layer through a via, the return current will also seek a new reference path. If the reference plane switches, and there is a lack of suitable stitching vias or decoupling paths near the signal via, the return current may detour, leading to an increased loop area. For high-speed signals, this path change increases the risk of impedance discontinuity and EMI.

Industry Optimization Solution: Sig-GND-GND-Sig Stackup

Sig - GND - GND - Sig is a common and relatively reliable stackup method for high-speed 4-layer boards because both the top and bottom signal layers are adjacent to continuous GND reference planes. In this way, when a signal crosses layers, coupled with appropriate GND stitching vias, it can provide a more direct path for the return current, thereby reducing the impedance variation and EMI risks caused by return path discontinuities.

The power distribution strategy for this structure also needs to be adjusted accordingly: after eliminating the dedicated solid power plane, modern multi-rail designs typically accomplish power distribution through polygon pours and wide traces on the top or bottom layers.

Engineering Suggestion: When adopting this stackup, the distance from the surface routing to the reference layer (dielectric thickness) directly affects the trace width requirements. It is recommended, in the early stages of design, to use the PCB Impedance Calculator provided by NextPCB to evaluate the Sig-GND-GND-Sig trace width parameters under different dielectric thicknesses, ensuring they fall within the PCB factory's standard manufacturing capabilities.

Analyzing Impedance Calculation Deviations and Lamination Realities in 6-Layer Boards

When using the built-in impedance calculators of EDA software (such as Altium Designer, KiCad), engineers typically base their calculations on nominal dielectric thicknesses and dielectric constants (Dk). However, in actual delivered 6-layer boards, the measured impedance often deviates from the theoretical value. This deviation usually stems from the combined effects of multiple factors, including material parameters, lamination processes, copper thickness, etching compensation, and copper surface roughness.

Resin Flow During the Lamination Process

In 6-layer board designs, L2 and L5 are usually large-area ground or power copper planes, while the adjacent L1 (Top) and L6 (Bottom) are often sparsely routed signal layers.

During the high-temperature and high-pressure PCB lamination process, the resin in the prepreg melts and flows to fill the gaps in the areas without copper foil on the L1 and L6 layers (i.e., the difference in copper retention rate). After lamination and curing, the actual dielectric thickness may deviate from the nominal thickness of the prepreg, and this deviation is affected by resin flow, copper foil distribution, and lamination conditions. Once the dielectric thickness decreases, the interlayer capacitance increases, and the characteristic impedance usually drops accordingly, so the measured value may be lower than the ideal result in the simulation.

Engineering Countermeasures

To avoid this deviation, engineers should take the following measures:

1. Obtain the factory's actual lamination parameters: Do not rely solely on the default values of EDA software. Refer to the Impedance Control Stackups which feature mature manufacturing data; these standard stackup specifications typically already account for typical factory lamination variations.
2. Choose professional impedance control services: For demanding high-speed buses, it is recommended to explicitly select the PCB Impedance Control Service when placing an order. Professional CAM engineers will calculate the actual copper retention rate based on your Gerber files, perform necessary line width compensation before production, and ultimately issue an impedance report through TDR testing.

How to Optimize Manufacturing Costs While Ensuring Signal Quality?

To control costs amidst fierce competition, many teams attempt to downgrade the layer count. However, besides reducing the number of layers, adopting the PCB manufacturer's standard stackups and materials is another effective and more reliable cost-reduction strategy.

According to the manufacturing specifications provided in the PCB Layer Stack-Up Guide, engineers can significantly reduce prototyping and mass production costs during the design phase through the following methods:

1. Prioritize mature and conventional lamination structures from the board factory
   Standard 4-layer or 6-layer boards typically adopt a relatively common symmetrical stackup method, using copper foil for the outer layers and a combination of core and prepreg for the inner layers to complete the lamination. Compared to non-standard, multi-core stacked schemes, these conventional structures are generally easier to manufacture, yield more stable results, and have more controllable overall costs. Therefore, during the design phase, prioritize aligning with the board factory's existing standard stackups rather than forcibly customizing complex structures for localized goals.
2. Maintain Z-axis symmetry in the stackup
   Asymmetrical stackup structures (for example, if the dielectric thickness of the upper half differs from the lower half, or if the copper thickness is asymmetrical) are highly prone to causing board warpage (Bow and Twist) after lamination and cooling due to the different coefficients of thermal expansion (CTE) of the materials. Warpage not only reduces SMT assembly yields but also increases the PCB factory's scrap rate, thereby driving up costs. Therefore, from the center layer to the top and bottom ends, the distribution of dielectric thickness and copper thickness must remain strictly symmetrical.
3. Avoid specifying non-standard prepreg thicknesses without adequate evaluation
   PCB factories typically offer several mature standard material combinations, such as 1080, 2116, and 7628. If a non-standard thickness is forcibly specified in pursuit of a specific impedance, it may increase the complexity of material procurement and trial laminations, thereby raising costs and extending delivery times. A more reliable approach is to prioritize the board factory's existing standard stackups, and then inversely adjust the trace width and spacing based on the actual stackup.

Standardized Manufacturing Instructions (Fab Note) Recommendations

To ensure the manufacturing results meet the expectations of high-speed design, when submitting Gerber data to the board factory, the following specification information should be included in the drill drawing or a separate Fab Note document:

• Layer sequence and attribute descriptions: Clearly list the sequence from L1 to Ln, and indicate the primary function of each layer (e.g., Routing, Solid GND, Split Power, etc.).
• Impedance control requirements table: Provide a clear table listing the network types that require impedance control. It must include:
  • Target Layer
  • Reference Layer
  • Trace Width / Spacing
  • Target Impedance and Tolerance (e.g., 90Ω Differential, ±10%)
• Fine-tuning authorization statement: To improve the impedance compliance rate, the following can be noted in the Fab Note: "The manufacturer may make necessary fine-adjustments to trace widths, spacing, and relevant dielectric parameters within its process capability range to meet target impedance requirements; if the adjustments exceed the conventional process range, please communicate via the Engineering Question (EQ) process first."

People Also Ask (Common Engineering Q&A)

Q: For handling high-speed signals on a 4-layer board, which stackup scheme performs more stably?
A: For 4-layer boards handling high-speed interfaces like USB 3.0, the Sig - GND - GND - Sig scheme generally provides better signal integrity. It eliminates the problem of return path discontinuity caused by reference plane changes when signals cross layers. However, the prerequisite is that the designer must be capable of properly planning the power copper pours and routing on the top and bottom layers.

Q: Why is the actual manufactured PCB impedance usually lower than the EDA software calculation?
A: EDA software calculations typically assume the dielectric layers are perfectly rectangular with uniform thickness. However, in physical manufacturing, the copper foil surface has roughness, and the resin in the prepreg will fill the gaps between the inner layer traces during lamination, causing the final cured dielectric thickness to be lower than the nominal value. A reduction in dielectric thickness directly leads to a decrease in characteristic impedance.

Q: In a stackup without a dedicated power plane, how do you ensure the Power Integrity (PI) of the chips?
A: After eliminating the solid power plane, power can be routed using broad polygon pours to ensure sufficient current-carrying capacity. More crucially, decoupling capacitors must be reasonably placed near the power pins of the chips to lower the alternating current (AC) impedance of the Power Delivery Network (PDN), thereby compensating for the loss of high-frequency response caused by the lack of interlayer parasitic capacitance.

Excellent hardware design is a combination of theoretical calculation and manufacturing processes. When planning high-speed PCBs, aligning stackup parameters with the manufacturer in advance can effectively mitigate late-stage risks. Engineers can leverage NextPCB's professional tools and standardized data to achieve optimal cost control while ensuring signal integrity.