The emergence of high-speed problems has brought greater challenges to hardware design. There are many logically correct designs. If not handled properly in actual PCB design, the entire design will fail. This situation is increasingly demanding high-speed networks. The field of communication is more obvious. Experts predict that in terms of future hardware circuit design overhead, the overhead of logic function design will be greatly reduced, and the overhead associated with high-speed design will account for 80% or more of the total overhead. High-speed problems have become one of the important factors for the success of system design.
Signal overshoot, undershoot, reflection, ringing, crosstalk, etc. due to high-speed problems will seriously affect the normal timing of the system. The reduction of system timing margin forces people to pay attention to various phenomena that affect the timing and quality of digital waveforms. When the timing is made harsh due to the increased speed, no matter how thorough understanding of the system principle is in advance, any neglect and simplification may have serious consequences for the system. In high-speed design, the impact of timing problems is more critical. This article will focus on timing analysis and simulation strategies in high-speed design.
Timing Analysis and Simulation of Common Clock Synchronization
In high-speed digital circuits, data transmission is generally controlled by an orderly transmission and reception of data signals through a clock. The chip can only send and receive data according to the specified timing. Too long signal delay or improper signal delay matching may lead to signal timing violation and confusing function. In low-speed systems, interconnect delays and ringing are negligible because the signal has sufficient time to reach a steady-state in such low-speed systems. However, in high-speed systems, the edge rate is increased, the system clock rate is increased, the transmission time of the signal between the devices and the synchronization preparation time are shortened, and the equivalent capacitance and inductance on the transmission line also delay and distort the digital conversion of the signal. In addition, factors such as signal delay mismatch will affect the setup and hold time of the chip, resulting in the chip not being able to correctly send and receive data, and the system will not work properly.
The so-called common clock synchronization means that during the data transmission process, the driver and the receiver on the bus share the same clock source, and the same clock buffer (CLOCK BUFFER) issues the in-phase clock to complete the data transmission. receive. Figure 1 shows a typical public clock synchronous data transmission and reception work. In Figure 1, the crystal CRYSTAL generates the output signal CLK_IN to the clock distributor CLOCK BUFFER. After the CLOCK BUFFER allocates the buffer, it sends two in-phase clocks. One is CLKB for the data output of DRIVER. The other is CLKA for sampling latch. Data sent by DRIVER to RECEIVER. The clock CLKB reaches DRIVER after a flight time (FLIGHT TIME) of Tflt_CLKB. The internal data of the DRIVER is latched by CLKB and appears on the output port of the DRIVER after TCO_DATA time. The output data then reaches the input port of the RECEIVER after a flight time Tflt_DATA. On the input port of RECEIVER, the other clock CLKA generated by CLOCK BUFFER (the delay is CLKA clock flight time, ie Tflt_CLKA) samples and latches the data from DRIVER, thus completing the COMMON CLOCK one clock cycle data transmission. process.
The above process shows that the data arriving at the RECEIVER is sampled by the rising edge of the next cycle of the clock. According to this, two necessary conditions for data transmission can be obtained: 1 The data of the RECEIVER input generally has the required setup time Setup, which Indicates that the data must be valid before the minimum time that the clock is valid. The time at which the data signal arrives at the input should be earlier than the clock signal so that the inequality satisfied by the setup time can be derived. 2 In order to successfully latch the data into the device, The data signal must be held at the input of the receiving chip for a sufficient period of time to ensure that the signal is correctly latched by the clock sample. This time is called the hold time, and the delay of CLKA must be less than the invalid time of the data (INVALID). The inequality that the hold time is satisfied can be obtained.
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