1. The actual PCB size, positioning device position, etc. are consistent with the process structure element map, and the device layout in the area where the device height is required to meet the requirements of the structural element map.
2. The outer frame of the board has a smooth curvature of 197 mils or is designed according to the structural dimensions.
3. The DIP switch, reset device, indicator light, etc. are in the right position, and the handle bar does not interfere with the surrounding devices.
4. The layout takes into account the appropriate increase in the space at the dense traces to avoid situations where the connection cannot be made.
5. The layout takes into account the smoothness of the overall routing and the main data flow is reasonable.
6. After the layout is completed, a 1:1 assembly drawing is provided for the projecter to check whether the device package selection is correct according to the device entity.
7. There are no short devices between the high devices, and no chip devices and short and small interposer devices are placed within 5 mm between devices with a height greater than 10 mm.
8. All the additional holes (ICT positioning holes 125mil, handle bar holes, elliptical holes and fiber holder holes) need to be added, and the settings are correct.
9. Adjust the pin assignments of the resistors, FPGAs, EPLDs, bus drivers, etc. according to the layout results to optimize the routing.
10. The wave pitch, device orientation, device pitch, device library, etc. of the wave soldering process take into account the requirements of wave soldering.
11. The surface containing the chip device has 3 positioning cursors and is placed in an "L" shape. Position the center of the cursor at a distance of more than 240 mils from the edge of the board.
12. When a high-speed optical module is included, the layout preferentially considers the optical port transceiver circuit.
13. Polar devices have a polar silkscreen logo. The same type of polar interposing components X and Y are the same in their respective directions.
14. The window has been considered to be retracted in the window opening and a suitable prohibited wiring area has been set.
15. The pin correspondence of the gusset connector has been confirmed to prevent the direction and orientation of the gusset connector from being reversed.
16. Ordinary plates have a 200 mil process edge; the left and right sides of the back plate have a process edge greater than 400 mils, and the upper and lower sides have a process edge greater than 680 mils. The device is placed in a position that does not conflict with the window opening position.
17. Device layout spacing meets assembly requirements: surface mount devices greater than 20 mils, ICs greater than 80 mils, and BGAs greater than 200 mils.
18. If special materials, special devices (such as 0.5mm BGA, etc.) and special processes are adopted, the delivery deadline and processability have been fully considered, and confirmed by PCB manufacturers and technicians.
19. For jigsaw processing, the layout is easy to imposition and facilitate PCB processing and assembly.
20. If there is an ICT test requirement, the layout will take into account the feasibility of the addition of ICT test points to avoid the difficulty of adding test points during the wiring phase.
21. All devices are clearly labeled, and no P*, REF, etc. are not clearly identified.
22. The crimping member is larger than 120 mils above the component surface of the crimping member, and there is no device in the penetration area of the soldering surface crimping member.
23. The preferred routing has been determined and all devices have been placed on the board.
24. The test points used for debugging have been added to the schematic and the position in the layout is appropriate.
25. Notched plate edges (shaped edges) should be filled in with the slots and stamp holes. The stamp holes are non-metallic, usually 40 mils in diameter and 16 mils apart.
26. The origin of the coordinates is the intersection of the left and lower extension lines of the frame, or the lower left pad of the lower left socket.