HDI PCB for AI Servers: Stackup, Via-in-Pad & Laser Drill Guide

Introduction

High-Density Interconnect (HDI) PCB technology is not optional for AI server boards—it is a prerequisite. The GPU and NVSwitch packages mounted on AI accelerator baseboards have BGA ball counts in the thousands to tens of thousands, at pitches of 0.65–0.8 mm, on packages up to 75 mm × 75 mm in size. Routing signal and power escape from the inner rows of these BGA arrays is geometrically impossible with conventional through-hole vias on boards of practical thickness and layer count. HDI microvias, via-in-pad structures, and sequential build-up lamination are the manufacturing technologies that make AI server PCB design physically realizable.

Understanding HDI at the process level matters for PCB designers and hardware engineers working in the AI server supply chain because HDI choices cascade through every other design and manufacturing decision: the HDI structure type determines the number of lamination cycles required; the lamination cycle count affects cost and lead time; the microvia diameter constrains minimum BGA pad pitch; and via-in-pad specification affects stencil design and reflow profile in downstream SMT assembly. This article covers each of these relationships systematically, with specific examples from H100, B200, and NVSwitch 4.0 board designs.

1. Table of Contents

• Introduction
• What Is HDI PCB Technology?
• Why AI Server PCBs Require HDI
• HDI Structure Types and When to Use Each
• Laser-Drilled Microvias: Process and Specifications
• Via-in-Pad (VIPPO): Design Rules and Manufacturing Process
• Any-Layer HDI (ELIC): The Most Complex Case
• Sequential Lamination: How HDI Boards Are Built
• Representative Stackup Examples for AI Server Boards
• Signal Integrity Considerations for HDI Via Structures
• Manufacturing Requirements and Qualification
• HDI vs Standard Through-Hole: Trade-off Summary
• FAQ

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What Is HDI PCB Technology?

HDI (High-Density Interconnect) is a PCB technology category defined by the use of laser-drilled microvias (diameter < 150 μm), fine trace/space geometries (≤ 100 μm / 100 μm), and sequential build-up layers (additional laminated layers added in multiple press cycles after the core is built) to achieve routing density that conventional through-hole via technology cannot provide.

The IPC/JPCA-2315 standard defines HDI by the presence of laser-drilled microvias with a diameter ≤ 150 μm that connect adjacent layers (blind vias from an outer layer to the first inner layer, or buried vias connecting inner layers without passing through the full board). This distinguishes HDI from standard multilayer PCBs where all vias are mechanically drilled through-holes spanning the full board thickness.

The key capability that HDI enables for AI server boards is BGA escape routing density: because microvias can be placed within BGA pads themselves (via-in-pad), and because microvias are much smaller than mechanical through-holes, significantly more escape routes can be packed under a fine-pitch BGA footprint. Without HDI, routing from the inner rows of a large GPU BGA would require so many through-hole vias that the anti-pad clearances in adjacent copper planes would disrupt the reference planes beneath critical NVLink and PCIe signal traces.

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Why AI Server PCBs Require HDI

Three specific characteristics of AI accelerator packages make HDI mandatory rather than optional:

1. Fine-pitch BGA with many signal rows: H100 SXM5 and B200 SXM6 packages use BGA pitch in the 0.65–0.8 mm range with package sizes up to 75 mm on a side. The innermost signal rows of such a package cannot be escaped to routing layers using conventional 0.2–0.3 mm diameter through-hole vias without violating minimum annular ring and anti-pad clearance rules. HDI microvias at 75–100 μm diameter, placed within BGA pads (via-in-pad), allow escape routing directly beneath the package footprint without the routing congestion that forces all signals to escape through the outermost peripheral rows only.

2. High layer count requiring build-up layers: AI server GPU baseboards use 20–32+ layers, as analyzed in detail at Why AI GPUs Require 30+ Layer HDI PCBs. At these layer counts, the board cannot be fabricated in a single lamination press cycle—the physical dimensions and registration accuracy requirements exceed what single-press lamination can achieve reliably. Sequential lamination in 3–5 press cycles, each adding HDI build-up layers, is the production approach for these boards.

3. Via stub elimination for high-speed signals: Through-hole vias on NVLink 4.0 and NVLink 5.0 signal traces create stubs that resonate at frequencies within the signal bandwidth, degrading channel insertion loss. While backdrilling can reduce stub length, replacing through-holes with blind HDI microvias on critical high-speed signal paths eliminates stubs entirely—the cleanest solution for NVLink 5.0 channels at 200 Gb/s per lane where even short stubs affect signal quality. The signal integrity consequences of via stubs at high speeds are covered in the context of NVLink in the NVLink PCB routing guide.

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HDI Structure Types and When to Use Each

HDI Type	Structure	Build-Up Layers per Side	Press Cycles	AI Server Application
Type I (1+N+1)	One build-up layer on each side of core; blind microvias from L1–L2 and L(n-1)–Ln	1	2	CPU motherboards; moderate-density BGA escape on data center server boards
Type II (2+N+2)	Two build-up layers per side; stacked or staggered microvias; buried vias in core	2	3	H100 HGX baseboard; fine-pitch SXM5 BGA escape; NVSwitch 3.0 breakout routing
Type III (3+N+3)	Three build-up layers per side; stacked microvias through all three build-up layers	3	4	B200 SXM6 baseboard; extreme BGA density; some NVSwitch 4.0 boards
Any-Layer HDI (ELIC)	Every layer interconnectable via stacked filled microvias; no full-board-thickness through-holes	All layers	5+	NVSwitch 4.0 boards in GB200 NVL72; maximum routing density at 32–40+ layers

The progression from 1+N+1 to any-layer HDI represents increasing routing density capability at increasing manufacturing complexity and cost. For AI server boards, the minimum HDI structure needed is determined by the BGA package pitch and pin count of the most demanding package on the board. A board carrying only standard server components (CPUs, DIMMs, PCIe switches) can use 1+N+1 HDI or even no HDI. A board carrying H100 SXM5 at 0.65 mm pitch requires at minimum 2+N+2 HDI. A board carrying NVSwitch 4.0 at the routing density required for the GB200 NVL72 switch fabric requires any-layer HDI.

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Laser-Drilled Microvias: Process and Specifications

Laser drilling is the manufacturing process that creates microvias in HDI build-up layers. Two laser types are used commercially:

CO₂ laser: The standard for 100–150 μm diameter microvias in glass-reinforced prepreg. CO₂ laser energy is absorbed by the resin and glass, ablating a cone-shaped cavity that stops when it reaches the copper target pad (copper reflects CO₂ wavelengths). CO₂ lasers provide high throughput (thousands of holes per second) and are available at most tier-1 PCB fabricators. Minimum achievable diameter is approximately 80–100 μm in standard prepreg.

UV laser (Nd:YAG or excimer): Used for < 75 μm microvias or for drilling through thin copper foil as well as resin (conformal mask drilling). UV lasers have lower throughput than CO₂ but achieve smaller minimum hole diameters (50–75 μm) and can drill through both resin and metal layers. Required for the smallest microvia diameters needed in any-layer HDI designs beneath very fine-pitch BGA packages.

Key microvia specifications for AI server HDI boards:

Parameter	Standard HDI (1+N+1)	H100-class (2+N+2)	B200/NVSwitch (3+N+3 or ELIC)
Microvia diameter	100–150 μm	85–100 μm	50–85 μm
Target pad diameter	250–350 μm	200–250 μm	150–200 μm
Capture pad diameter	300–400 μm	200–300 μm	150–225 μm
Stacked via alignment tolerance	± 50 μm	± 25–35 μm	± 15–25 μm
Aspect ratio (depth/diameter)	0.75:1 max	0.9:1 max	1:1 max
Laser type	CO2	CO2 or UV	UV (for < 75 μm)

After laser drilling, residual resin debris (desmear) must be removed from the via cavity by chemical or plasma cleaning before copper plating. For HDI boards, the desmear process must be controlled carefully to avoid over-etching the thin dielectric layers of the build-up structure while achieving complete cavity cleaning. Incomplete desmear creates high-resistance microvia connections that may pass initial electrical test but fail under thermal cycling in service.

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Via-in-Pad (VIPPO): Design Rules and Manufacturing Process

Via-in-Pad Plated Over (VIPPO) places a microvia (or a filled through-hole via) directly within a BGA pad rather than adjacent to it. This is the technique that allows signal escape routing from the innermost rows of fine-pitch GPU and NVSwitch BGA packages where there is literally no space for a trace segment between pad edge and via pad edge at the required pitch.

The VIPPO manufacturing process sequence:

1. Drill: Laser drill (for microvia) or mechanical drill (for through-hole) creates the via within the pad area
2. Plate: Electroless copper followed by electrolytic copper plate the via barrel to IPC specification (≥ 18 μm in the via barrel)
3. Fill: Conductive or non-conductive epoxy is screen-printed or vacuum-forced into the via opening; fill must be void-free and extend slightly proud of the pad surface before grinding
4. Cure: Epoxy is thermally cured at 150–180°C; cure shrinkage must be < 3% volumetric to prevent dimple formation after cure
5. Planarize: The cured epoxy is mechanically ground flush with the copper pad surface; target planarity is < 10 μm deviation across the pad area
6. Cap plate: Additional copper (10–15 μm) is electroplated over the filled and planarized via, creating a solid, flat pad surface for solder joint formation
7. Surface finish: ENIG (Electroless Nickel Immersion Gold) or ENEPIG applied over all SMT pads including VIPPO pads; gold thickness and adhesion on via-in-pad areas must be verified against bridging or black pad risk

The planarity of the cap-plated VIPPO pad is critical for GPU BGA assembly. A dimple (concave) surface reduces paste volume printed on the pad; a protrusion (convex) surface causes the BGA ball to sit proud of the paste, increasing the risk of head-on-pillow defects. The reflow and assembly implications of via-in-pad quality are covered in the GPU assembly context at GPU Board Assembly: Manufacturing Challenges.

Conductive vs non-conductive epoxy fill: Conductive (silver-filled) epoxy provides electrical continuity through the fill material as a backup to the via wall plating, and provides better thermal conductivity for vias beneath high-power components. Non-conductive epoxy is lower cost and adequate for signal vias where via wall plating provides the electrical path. For power delivery vias beneath GPU packages, conductive fill is preferred. For signal vias, either fill type is acceptable.

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Any-Layer HDI (ELIC): The Most Complex Case

Any-Layer HDI, also called ELIC (Every Layer Interconnect), takes HDI to its logical conclusion: every layer in the stackup is interconnected by stacked, copper-filled microvias. There are no traditional mechanical through-holes spanning the full board thickness. This eliminates the stub resonance problem entirely (stacked microvias have no stub below the connection point) and allows via structures to be placed on any layer to any other layer with the same small footprint as a single-layer microvia.

ELIC is reserved for the highest-density applications in commercial PCB production. In AI server hardware, it is required for NVSwitch 4.0 boards in the GB200 NVL72 where the combination of 32–40+ layers, very fine-pitch NVSwitch 4.0 BGA packages, and extremely high NVLink 5.0 differential pair routing density exceeds what 3+N+3 sequential build-up HDI can achieve within the board thickness constraints. The full architectural context for why NVSwitch boards reach this complexity is explained in the NVSwitch guide and the Blackwell architecture overview.

ELIC manufacturing requires:

• 5 or more sequential lamination press cycles (one for each pair of added layers)
• Copper-filled microvia technology where each microvia is completely filled with electroplated copper (not just wall-plated) to provide a flat, solderable surface for the next stacked microvia above it
• Stacked via alignment of ± 15–25 μm across all layers, requiring optical registration systems rather than mechanical tooling pins for each sequential lamination
• Controlled plating chemistry to achieve void-free copper fill in microvias at aspect ratios approaching 1:1

Very few PCB fabricators worldwide have qualified ELIC production capability for 32+ layer AI server boards. ELIC is manufactured by a small number of Tier-1 suppliers with dedicated process lines and years of accumulated qualification data.

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Sequential Lamination: How HDI Boards Are Built

Sequential lamination is the fabrication approach that enables HDI build-up structures. Rather than pressing all layers simultaneously in a single press cycle, HDI boards are built in stages: the core is pressed first, then build-up layers are added one or two at a time in additional press cycles, with laser drilling and copper plating between each cycle.

A 2+N+2 HDI board (two build-up layers per side of core) requires three press cycles:

1. Core press: Inner layer pairs and prepreg are stacked and pressed to form the N-layer core; mechanical drilling of core through-holes; copper plating of core vias
2. First build-up press: First build-up prepreg layer added to each side of the core with copper foil; pressed and cured; laser drilling of first-level microvias (connecting build-up layer 1 to core outer layer); copper plating
3. Second build-up press: Second build-up prepreg layer added to each side; pressed and cured; laser drilling of second-level microvias (connecting build-up layer 2 to build-up layer 1); copper plating; outer layer imaging and etching; surface finish

Each press cycle introduces thermal stress on previously processed layers. The cumulative effect of 3–5 press cycles at 180–200°C is a significant concern for laminate integrity and layer registration. Low-loss laminates like Megtron 6E and Megtron 7 are formulated for multi-cycle press compatibility, but fabricators must validate their press cycles specifically for each material combination used in a hybrid stackup. The material selection and hybrid stackup design framework for AI server boards is covered at High-Speed PCB Materials for AI Servers.

Registration accuracy degrades with each additional press cycle because thermal expansion differences between layers cause cumulative dimensional shift. State-of-the-art fabricators achieve ± 25–50 μm layer-to-layer registration across all cycles for AI server board production; registration beyond ± 75 μm at any layer causes via misalignment that degrades electrical reliability.

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Representative Stackup Examples for AI Server Boards

The following representative stackup descriptions illustrate how HDI structures are applied at different AI server complexity tiers.

CPU Motherboard (1+N+1 HDI, 14 layers): Two build-up layers (one per side) over a 12-layer core. Build-up layers provide BGA escape for CPU packages (AM5, LGA4677). Core handles DDR5 routing, PCIe Gen5 signal layers with Megtron 6E, power and ground planes. Single build-up laser drill cycle after core press. Microvias at 100–125 μm diameter. Via-in-pad on select CPU package pads. Total: 2 press cycles.

H100 HGX Baseboard (2+N+2 HDI, 22 layers): Four build-up layers (two per side) over an 18-layer core. Build-up layers provide BGA escape for SXM5 socket pads and NVSwitch 3.0 outer BGA rows. Core handles NVLink 4.0 signal routing (Megtron 6E, VLP copper), power planes (heavy copper for GPU PDN), and PCIe Gen5 routing. Microvias at 85–100 μm diameter; stacked microvias on build-up layers 1–2 for inner BGA rows. Via-in-pad on SXM5 and NVSwitch packages. Total: 3 press cycles.

B200 Compute Tray Baseboard (3+N+3 HDI, 30 layers): Six build-up layers (three per side) over a 24-layer core. Three build-up layers per side required for SXM6 BGA escape at the higher pin count and tighter effective pitch of the B200 dual-die CoWoS package. Core routes NVLink 5.0 (Megtron 7, HVLP copper), PCIe Gen6, and 48 V power delivery planes. Microvias at 75–85 μm on outer build-up layers; stacked microvias through all three build-up layers for innermost BGA rows. Total: 4 press cycles.

NVSwitch 4.0 Board (Any-Layer HDI / ELIC, 36 layers): All 36 layers interconnected by stacked copper-filled microvias. No full-board-thickness through-holes. UV laser drilling for < 75 μm microvias. 5+ sequential lamination cycles. Megtron 7 with HVLP copper throughout NVLink 5.0 signal layers. This board type represents the current frontier of commercial HDI manufacturing capability.

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Signal Integrity Considerations for HDI Via Structures

HDI microvias and via-in-pad structures have different signal integrity characteristics than through-hole vias, generally more favorable for high-speed signals:

• No stub resonance: Blind microvias connect only two adjacent layers and have no unused barrel below the connection point. This eliminates the stub resonance notches that degrade NVLink and PCIe channel insertion loss with through-hole vias, removing the need for backdrilling on microvia-connected signals
• Lower shunt capacitance: Microvia pads are much smaller than through-hole via pads (150–200 μm vs 400–600 μm for typical through-holes). Smaller pads have lower parasitic capacitance at the via transition, reducing the impedance dip at the via and improving return loss
• Smaller anti-pad clearance: The smaller microvia anti-pad (clearance in adjacent copper planes) disrupts the reference plane less than a through-hole anti-pad, maintaining better impedance continuity along the adjacent signal layers
• Stacked via inductance: Stacked microvias (multiple microvias stacked vertically to traverse multiple build-up layers) have higher inductance per unit length than a single equivalent via, which must be accounted for in high-speed signal path simulation. The inductance is proportional to the number of stacked vias × pitch between layers

For NVLink 5.0 channels at 200 Gb/s per lane, the ideal via solution is stacked microvias with copper fill, as used in ELIC designs, which provides the cleanest possible launch geometry with minimal inductance and no stub resonance. The combined signal integrity design for NVLink 5.0 routing—including via design, material selection, and trace geometry—is covered comprehensively in the AI Accelerator PCB Design Guide.

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Manufacturing Requirements and Qualification

HDI PCB manufacturing for AI server boards requires capabilities that not all commercial PCB fabricators possess. The key capability requirements are:

Laser drilling systems: CO₂ laser for standard microvias (≥ 85 μm); UV laser (Nd:YAG or excimer) for < 75 μm microvias in any-layer HDI. Both types require precise beam focusing, pulse energy control, and in-process inspection of hole quality (diameter, circularity, wall angle) on production panels.

Sequential lamination presses: Multi-cycle lamination capability with temperature, pressure, and vacuum control qualified for low-loss laminates (Megtron 6E, Megtron 7). Each press cycle introduces cumulative dimensional change; fabricators must have characterized the dimensional shrinkage/expansion behavior of each material through multiple lamination cycles and compensate in the artwork scaling used for each layer.

Copper fill plating for ELIC: Any-layer HDI requires microvia copper fill plating chemistry that achieves void-free, flat-topped copper deposition in microvias at aspect ratios up to 1:1. Standard via-wall plating chemistry is not adequate; dedicated copper fill plating baths with additives that promote bottom-up fill growth (rather than conformal deposition) are required.

Registration measurement and verification: Layer-to-layer registration must be measured at multiple panel locations after each lamination cycle; X-ray measurement of microvia center positions relative to target pad centers is the standard verification method. Panels with registration exceeding ± 50 μm at any measured location are flagged for engineer review before proceeding to subsequent cycles.

IPC qualification: AI server HDI boards should be fabricated to IPC Class 3 (High Reliability) for all fabrication parameters: minimum via barrel copper thickness (≥ 18 μm), minimum annular ring (≥ 50 μm for microvias), and acceptable hole quality per IPC-A-600 Class 3 criteria. NextPCB's Advanced PCB capabilities cover the full range of IPC Class 3 HDI production for AI server programs.

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HDI vs Standard Through-Hole: Trade-off Summary

Parameter	Standard Through-Hole Via	HDI Microvia (Blind)	Via-in-Pad (VIPPO)	Any-Layer HDI (ELIC)
Via diameter	200–400 μm	75–150 μm	75–150 μm (within pad)	50–100 μm
Layers connected	All layers (full board thickness)	Adjacent layers only	Adjacent layers only	Any two layers (via stacking)
Stub problem	Yes (requires backdrilling for high speed)	No stub	No stub	No stub
Reference plane disruption	Moderate to large (anti-pad 400–700 μm)	Small (anti-pad 150–300 μm)	Small	Minimal
Routing density beneath BGA	Low (limited by anti-pad congestion)	High	Very high (pad area fully utilized)	Maximum
Manufacturing cost (relative)	1×	2–3×	3–4×	8–15×
Lead time impact	Baseline	+3–5 days per build-up cycle	+2–3 days (fill, grind, plate)	+10–20 days total
AI server applications	Non-critical signals; power planes	BGA escape; high-speed signal transitions	Fine-pitch GPU/NVSwitch BGA inner rows	NVSwitch 4.0 boards; 32–40L extreme density

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FAQ

What is the difference between a blind via and a buried via?
A blind via connects an outer layer to one or more inner layers without passing through the full board thickness—it is “blind” because it is visible from one surface but not the other. A buried via connects inner layers only and is not visible from either outer surface. In HDI AI server boards, blind microvias from the outer build-up layer to the first inner layer are the most common structure; buried vias in the core connect inner layers within the core stackup. Both types are fabricated by laser (blind in build-up layers) or mechanical drill (buried in core), and both require sequential lamination to access.

Does via-in-pad require different solder paste stencil design?
Yes. Via-in-pad structures affect stencil aperture design in two ways. First, the via opening (even after fill and cap plating) may have slightly different solder wetting characteristics than a solid copper pad; some designs specify slightly larger apertures over VIPPO pads to compensate for any minor wetting variation. Second, for through-hole via-in-pad where the via is not perfectly planarized, the aperture geometry must be carefully sized to avoid paste bridging between the VIPPO pad and adjacent pads. The solder paste and reflow requirements for GPU BGA assembly including VIPPO pads are detailed at GPU Board Assembly: Manufacturing Challenges.

Can HDI microvias carry high current for power delivery?
Yes, with limitations. A fully copper-filled microvia at 100 μm diameter can carry approximately 1–2 A continuously. For GPU power delivery applications requiring hundreds of amperes, arrays of thermal vias (dense grids of through-holes or microvias beneath GPU packages) are used to distribute the current across many vias in parallel. Via-in-pad power delivery structures under GPU packages are filled with conductive epoxy and copper-capped to provide both electrical current-carrying capacity and thermal conduction from the GPU package through the PCB to the cold plate structure. The power delivery requirements for AI server GPU packages are analyzed in depth in the AI Accelerator PCB Design Guide.

How many build-up layers are needed for a B200 baseboard?
B200 SXM6 packages require 3+N+3 HDI—three build-up layers per side of the core—to achieve adequate BGA escape routing density for the SXM6 socket at B200's pin count and pitch. The three build-up layers per side add 6 layers to the total count (3 on top, 3 on bottom) above the core layer count; a B200 baseboard with a 24-layer core uses 30 total layers with 3+N+3 HDI. Some designs optimize to 2+N+2 by using more aggressive via-in-pad density in the inner build-up layers, but 3+N+3 is the more common production approach for B200 baseboards.

What is the minimum fabricator qualification level for AI server HDI boards?
AI server HDI boards should be fabricated by a manufacturer qualified to IPC-6012 Class 3, with specifically demonstrated capability for the relevant HDI structure type. For 2+N+2 HDI (H100-class boards), fabricators should provide sample cross-sections demonstrating microvia copper fill quality, stacked via alignment (< 35 μm), and VIPPO planarization (< 10 μm deviation). For any-layer HDI (NVSwitch 4.0 boards), demonstrated production history on ELIC structures at 32+ layers is the appropriate qualification evidence. NextPCB maintains IPC Class 3 certification with demonstrated HDI capability; qualification documentation is available at the NextPCB quality certifications page.

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Need HDI PCB Manufacturing for AI Server Programs?

From 1+N+1 HDI for CPU motherboards to 3+N+3 and any-layer HDI for GPU baseboards and NVSwitch boards, NextPCB provides the sequential lamination capability, laser drilling systems, copper fill plating, VIPPO processing, and IPC Class 3 quality standards required for AI server HDI production. Use our online tools to start your evaluation: check your Gerber files with the free Gerber viewer, calculate controlled impedance targets with the impedance calculator, or go straight to a quote.

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