Properly placing a capacitor of appropriate capacity near the power supply pin of the IC can make the output voltage of the IC jump faster. However, the problem is not here. Due to the finite frequency response of the capacitor, this makes it impossible for the capacitor to generate the harmonic power required to cleanly drive the IC output over the full frequency band. In addition, the transient voltage developed on the power bus forms a voltage drop across the inductor of the decoupling path, which is the primary source of common-mode EMI interference. How should we solve these problems?
As far as the ICs on our boards are concerned, the power plane around the IC can be thought of as an excellent high-frequency capacitor that collects the energy that is leaked by discrete capacitors that provide high-frequency energy for clean outputs. In addition, the excellent power supply layer has a small inductance, so that the transient signal synthesized by the inductor is also small, thereby reducing common mode EMI.
Of course, the wiring from the power plane to the IC power supply pin must be as short as possible because the rising edge of the digital signal is getting faster and faster, preferably directly to the pad where the IC power supply pin is located. This is discussed separately.
To control common-mode EMI, the power plane must be decoupled and have a low enough inductance. This power plane must be a well-designed pair of power planes. Someone may ask, to what extent is it good? The answer to the question depends on the layering of the power supply, the material between the layers, and the operating frequency (ie, the function of the rise time of the IC). Typically, the power supply is layered at 6 mils and the mezzanine is FR4. The equivalent capacitance per square inch of power plane is approximately 75 pF. Obviously, the smaller the layer spacing, the larger the capacitance.
There are not many devices with a rise time of 100 to 300 ps, but according to the current development speed of ICs, devices with a rise time of 100 to 300 ps will occupy a high proportion. For circuits with 100 to 300 ps rise time, the 3 mil layer spacing will no longer be suitable for most applications. At that time, it was necessary to use a layering technique with a layer spacing of less than 1 mil and to replace the FR4 dielectric material with a material having a high dielectric constant. Ceramics and ceramics now meet the design requirements of 100 to 300 ps rise time circuits.
Although new materials and methods may be used in the future, for today's common 1 to 3 ns rise time circuits, 3 to 6 mil layer spacing and FR4 dielectric materials, it is usually sufficient to handle high-end harmonics and make the transient signal low enough. That said, common mode EMI can be reduced very low. The PCB layered stack design example given here will assume a layer spacing of 3 to 6 mils.
From the perspective of signal routing, a good stratification strategy should be to place all signal traces in one or several layers, which are next to the power or ground plane. For the power supply, a good stratification strategy should be that the power layer is adjacent to the ground plane, and the distance between the power plane and the ground plane is as small as possible. This is what we call the "layering" strategy.
Given that most engineers design boards that are 62 mils thick and have no blind vias or buried vias, the discussion of board delamination and stacking is limited to this. For boards with too much thickness difference, the layering scheme recommended in this paper may not be ideal. In addition, the processing method of the circuit board with blind holes or buried holes is different, and the layering method of this paper is not applicable.
The thickness, via process, and number of layers in the board design are not critical to solving the problem. Excellent layered stacking ensures bypass and decoupling of the power busbars and minimizes transient voltages on the power or ground plane. The key to shielding the signal and the electromagnetic field of the power supply. Ideally, there should be an insulating isolation between the signal trace layer and its return ground plane, and the matching layer spacing (or more than one pair) should be as small as possible. Based on these basic concepts and principles, it is possible to design a board that always meets the design requirements. Now, IC's rise time is already short and will be shorter, and the techniques discussed in this article are essential to address EMI shielding issues.
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