Ensure that the clock drive capability should not be realized through protection, generally using a clock drive chip. Generally, the clock driving power is due to multiple clock loads. A clock drive chip is used to turn a clock signal into several points, using point-to-point connections. In addition to the basic matching between the load and the load, the selection of the driver chip can be used to calculate the time delay in the drive chip when the signal is satisfied (the general clock is a valid signal).
37. If a single clock signal board is used, what kind of interface is normally adopted to ensure that the transmission of the clock signal is less affected?
The shorter the clock signal, the smaller the transmission line effect. The use of a separate clock signal board will increase the length of the signal wiring. And the single board grounding power supply is also a problem. If long-distance transmission is needed, a differential signal is recommended. The LVDS signal can satisfy the driving capability requirement, but your clock is not too fast and unnecessary.
38. 27M, SDRAM clock line (80M-90M), the two or three harmonics of these clock lines are just in VHF band, and interfere with the high frequency when the receiver enters high frequency. Are there any good ways besides short line length?
If the three harmonic is large and the two harmonic is small, it may be because the duty cycle of the signal is 50%, because there is no even harmonics in the case. It is necessary to modify the duty ratio of the signal. In addition, if the unidirectional clock signal is used, the source end series matching is usually adopted. This inhibits the two reflections but does not affect the clock rate. The matching value of the source end can be obtained by the following formula.
39. What is the topology of the line?
Topology, some are also called routing order. for the wiring sequence of multi-port connected networks.
40. How to adjust the topological structure of the line to improve signal integrity?
The direction of this kind of network signal is very complex, because it is not the same for unidirectional, bidirectional signal, different level type signal, and it is difficult to say which topology is good for the quality of the signal. Moreover, the topology used for pre emulation is very demanding for engineers and requires an understanding of circuit principles, signal types, and even wiring difficulties.
41. How can we reduce the EMI problem by arranging layers?
First of all, EMI must consider from the system, and PCB alone can not solve the problem. Stacking for EMI, I think it is mainly to provide the shortest signal return path, reduce the coupling area, and suppress differential mode interference. In addition, the formation is tightly coupled with the power supply layer, which is better than the power layer epitaxy in restraining the common-mode interference.
42. Why do you want to make copper?
There are several reasons for the general spread of copper. 1, EMC. will play a shielding role for a large areas of ground or power supply. There are some special ways, such as PGND, to play a protective role. 2, PCB process requirements. Generally, in order to ensure the electroplating effect or laminates do not deform, copper is laid on the PCB layer with less wiring. 3, signal integrity requires a complete reflux path for high frequency digital signals and reduces the wiring of the DC network. Of course, there is heat dissipation, special device installation requirements, and so on.
43. In a system that contains DSP and PLD, what are the problems to be noted when routing?
Look at the ratio of your signal rate to the length of the wiring. If the time delay and the signal variation of the signal on the transmission line are comparable with time, the signal integrity problem must be considered. In addition, for multiple DSP, clock, and data signal, the signal quality and timing need to be concerned.
44. Are there any other good tools besides Protel tool wiring?
As for tools, in addition to PROTEL, there are many wiring tools, such as MENTOR's WG2000, EN2000 series and Power PCB, Cadence's Allegro, zuken cadstar, cr5000, and so on.
45. What is the "signal backflow path"?
The signal recirculation path, that is, return current. When the high-speed digital signal is transmitted, the flow of the signal is from the drive along the PCB transmission line to the load, and then the load along the ground or the power supply is returned to the drive end through the shortest path. The return signal on the ground or power is called the signal return path. Dr.Johson explains in his book that high-frequency signal transmission is actually a process of charging a dielectric capacitor sandwiched between the transmission line and the DC layer. SI analyses the electromagnetic characteristics of the enclosure and their coupling.