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Detailed ESD in PCB Design
Posted:03:22 PM March 13, 2018 writer: G

1. Circuit loop

Current flows through the induction into the circuit loops, which are closed and have varying magnetic flux. The magnitude of the current is proportional to the area of ??the ring. Larger loops contain more magnetic flux and thus induce stronger currents in the circuit. Therefore, the loop area must be reduced.

The most common loop is formed by power and ground. Where possible, multilayer PCB designs with power and ground planes can be used. Multi-layer boards not only minimize the loop area between the power supply and ground, but also reduce the high-frequency EMI field generated by ESD pulses.

If a multi-layer circuit board cannot be used, the lines for the power line and the ground must be connected in the form of a grid as shown in FIG. The grid connection can function as a power and ground plane, with vias connecting the traces of the layers, and the via spacing in each direction should be within 6 cm. In addition, when wiring, it is also possible to reduce the loop area by placing the power supply and the ground trace as close together as possible.

Another way to reduce loop area and sense current is to reduce parallel paths between interconnect devices.

When a signal cable longer than 30 cm must be used, a protection cable can be used. A better approach is to place a stratum near the signal line. The signal line should be within 13 mm from the protection line or ground layer.

Cross each sensor's long signal line (>30 cm) or power line with its ground line. Crossed lines must be arranged at regular intervals from top to bottom or from left to right.

2. Circuit connection length

The long signal line can also be used as an antenna for receiving ESD pulse energy. Using a shorter signal line as much as possible can reduce the efficiency of the signal line as an ESD electromagnetic field antenna.

As far as possible, the interconnected devices are placed adjacent to each other to reduce the printed trace length of the interconnect.

3. Earth charge injection

Direct discharge from the ESD to the ground plane can damage sensitive circuitry. When using TVS diodes, one or more high-frequency bypass capacitors must also be used. These capacitors are placed between the power supply of the fragile component and the ground. The bypass capacitor reduces charge injection and maintains the voltage difference between the power supply and the ground port.

The TVS diverts the induced current and maintains the potential difference of the TVS clamp voltage. The TVS and the capacitor should be placed as close as possible to the protected IC. The length of the TVS to ground path and capacitor pins must be the shortest to reduce parasitic inductance effects.

The connector must be mounted to the copper platinum layer on the PCB. Ideally, the copper-platinum layer must be isolated from the PCB's ground plane and connected to the pad via a short line.

4. Other guidelines for PCB design

1. Avoid placing important signal lines on the edge of the PCB, such as clocks and reset signals;

2. Set the unused portion of the PCB to the ground plane.

3. The distance between chassis ground and signal line is at least 4mm;

4. Keep the length and width ratio of the chassis ground wire less than 5:1 to reduce the inductance effect;

5. Use TVS diodes to protect all external connections;

5. Parasitic inductance in the protection circuit

Parasitic inductance in the TVS diode path can cause severe voltage overshoot in the event of an ESD event. Despite the use of a TVS diode, an excessive overshoot voltage may still exceed the damage voltage threshold of the protected IC due to the induced voltage VL=L di/dt across the inductive load.

The total voltage that the protection circuit withstands is the sum of the clamp voltage of the TVS diode and the voltage generated by the parasitic inductance, VT=VC+VL. An ESD transient induced current peaks in less than 1 ns (according to IEC 61000-4-2), assuming a lead inductance of 20nH per inch, a quarter-inch line, and an overshoot voltage of 50V 10A pulse. The empirical design criteria is to design the shunt path as short as possible to reduce parasitic inductance effects.

All inductive paths must consider the use of ground loops, the path between the TVS and the protected signal line, and the path from the connector to the TVS device. The protected signal line should be directly connected to the ground plane. If there is no ground plane, the connection of the ground loop should be as short as possible. The distance between the ground of the TVS diode and the ground point of the circuit to be protected should be as short as possible to reduce the parasitic inductance of the ground plane.

Finally, TVS devices should be placed as close to the connector as possible to reduce transient coupling into nearby lines. Although there is no direct access to the connector, this secondary radiation effect can also lead to turbulence in other parts of the board.

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