And the data delay:
To meet the data retention time, you must have:
Expand, organize and consider the clock jitter Tjitter and other factors, you can get the following relationship:
In equation (2), the first bracket is still the maximum phase difference between the clock chip CLOCK BUFFER output clock; the second bracket can continue to be understood as the clock chip output two clocks CLKA, CLKB reach RECEIVER and DRIVER respectively The maximum delay difference; to meet the data retention time, there are only two actual adjustable parts, namely Tflt_CLKB_MIN-Tflt_CLKA_MAX and Tflt_DATA_SWITCH_DELAY_MIN. From the standpoint of satisfying the hold time, Tflt_CLKB_MIN and Tflt_DATA_SWITCH_DELAY_MIN should be as large as possible, and Tflt_CLKA_MAX should be as small as possible. That is to say, if the retention time is to be satisfied, the reception clock should be made earlier, and the data should be invalid later.
In order to receive data correctly and correctly, it is necessary to comprehensively consider the setup time and hold time of the data, that is, satisfy both equations (1) and (2). Analysis of these two inequalities shows that there are only three ways to adjust: the transmit clock delay, the receive clock delay, and the data delay. The adjustment scheme can be performed by first assuming that the transmit clock delay is strictly equal to the receive clock delay, ie Tflt_CLKA_MIN-Tflt_CLKB_MAX =0 and Tflt_CLKB_MIN-Tflt_CLKA_MAX =0 (the timing offset due to the assumptions of these two equations will be considered later) Then, the delay range of the data can be obtained through simulation. If the data delay has no solution, the above two equations are returned, and the transmission clock delay or the reception clock delay is adjusted. The following is an example of GLINK bus common clock synchronous data transmission and reception in a broadband network switch: first assume that the transmission clock delay is strictly equal to the reception clock delay, and then determine the delay range of the data, substituting the parameters, (1) and (2) respectively Becomes:
At the inequality prompt, combined with the actual layout of the PCB, determine Tflt_DATA_SETTLE_DELAY_MAX<1.1; tflt_data_switch_delay_min>-0.1, and the remaining 0.4 ns is allocated to the time difference and Tmargin of the two clocks. The topology is extracted in SPECCTRAQUEST and signal integrity simulation is performed to determine the length and topology of each segment. Full scan simulation of this structure (12 combinations), get Tflt_DATA_SETTLE_DELAY_MAX=1.0825 Tflt_DATA_SWITCH_DELAY_MIN =-0.0835004, which meets the determined 1.1 and
-0.1 range indicator. Therefore, the constraint rule of the GLINK bus data line can be obtained: 1 the delay of the matching resistor to the transmitting end should not be greater than 0.1 ns;
2 Data lines must be matched in 0.1 ns, that is, each data line must be between 0.65 ns and 0.75 ns. With the above constraint rules, you can guide the wiring.
Let's consider the impact of the rigid specification Tflt_CLKA_MIN-Tflt_CLKB_MAX=0 and Tflt_CLKB_MIN-Tflt_CLKA_MAX=0. The transmission clock and the reception clock are constrained in advance to be equal in length (matching in 0.02 ns in actual operation). In the CADENCE environment, clock simulation is performed to obtain the result: |Tflt_CLKA_MIN-Tflt_CLKB_MA interconnection X|<0.2 and |tflt_clkb_min-tflt_clka_max|<0.2 . It can be seen that the margin left for tmargin is 0.2 ns. < p="">
The final simulation results are: 1 the delay of the matching resistor to the transmitter should not be greater than 0.1 ns; 2 the data line is matched with 0.1 ns, that is, each data line must be between 0.65 ns and 0.75 ns; 3 transmit clock and receive The clock matches the equal length at 0.02 ns; 4Tmargin = 0.2 ns. SPECCTRAQUEST or ALLEGRO can be imported into CONSTRAINS MANAGER with the above topology template and constraint rules. When these design constraint rules are set, you can use the autorouter for rule-driven automatic routing or manual tuning.
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