Three factors are related to this effect: the magnitude of the impedance change, the rise time of the signal, and the delay of the signal on the narrow line.
First, the magnitude of the impedance change will be discussed. Many circuit designs require that the reflected noise be less than 5% of the voltage swing (this is related to the noise budget on the signal), based on the reflection coefficient formula:
The approximate rate of change of the impedance can be calculated as:
As you may know, the typical indicator of impedance on the board is +/10%, the root cause is here.
If the impedance change occurs only once, for example, after the line width is changed from 8 mils to 6 mils, the 6 mil width is maintained. To achieve the noise budget requirement that the signal reflection noise at the catastrophe does not exceed 5% of the voltage swing, the impedance change must be less than 10%. This is sometimes difficult to do. Take the case of the microstrip line on the FR4 board as an example. Let's calculate it. If the line width is 8 mils, the thickness between the line and the reference plane is 4 mils and the characteristic impedance is 46.5 ohms. After the line width is changed to 6 mils, the characteristic impedance becomes 54.2 ohms, and the impedance change rate reaches 20%. The amplitude of the reflected signal must exceed the standard. As for how much impact on the signal, it is also related to the signal rise time and the delay of the signal from the drive end to the reflection point. But at least this is a potential problem. Fortunately, the problem can be solved by impedance matching termination.
If the impedance change occurs twice, for example, after the line width is changed from 8 mils to 6 mils, it is pulled back 2 cm and then changed back to 8 mils. Then, reflection occurs at both end points of a 2cm long 6mil wide line. Once the impedance is increased, positive reflection occurs, and then the impedance becomes small and negative reflection occurs. If the two reflection intervals are short enough, the two reflections may cancel each other out, thus reducing the effect. Assuming that the transmitted signal is 1V, the first positive reflection has 0.2V reflected, 1.2V continues to transmit forward, and the second reflection has 0.2*1.2 = 0.24v reflected back. Assuming that the length of the 6mil line is extremely short and the two reflections occur almost simultaneously, the total reflected voltage is only 0.04V, which is less than 5% of the noise budget requirement. Therefore, whether or not this reflection affects the signal has a large influence on the delay at the impedance change and the rise time of the signal. Research and experiments have shown that as long as the delay at the impedance change is less than 20% of the signal rise time, the reflected signal will not cause problems. If the signal rise time is 1 ns, then the delay at the impedance change is less than 0.2 ns for 1.2 inches, and reflection does not cause problems. That is to say, for the case of this example, the length of the 6 mil wide trace is less than 3 cm and there is no problem.
When the PCB trace width changes, it should be carefully analyzed according to the actual situation, whether it will affect. The parameters to be concerned are three: how big is the impedance change, what is the signal rise time, and how long the neck portion of the line width changes. According to the above method, it is estimated roughly, and a certain margin is appropriately reserved. If possible, try to reduce the length of the neck.
It should be pointed out that in actual PCB processing, the parameters cannot be as accurate as in theory. The theory can provide guidance for our design, but it cannot be copied and cannot be dogmatic. After all, this is a practical science. The estimated value should be appropriately revised according to the actual situation and applied to the design. If you feel that you are not experienced enough, then keep it conservative and then adjust it according to the manufacturing cost.
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