Here are 24 tips to reduce noise and electromagnetic interference in PCB design after years of design:
(1) Can use low-speed chips, do not use high-speed, high-speed chips used in the key areas.
(2) A resistor string can be used to reduce the upper and lower edge of the control circuit toggle rate.
(3) Try to provide some kind of relay for the damping.
(4) Use the lowest frequency clock that meets the system requirements.
(5) Clock generator as close as possible to the clock device. Quartz crystal oscillator shell to ground.
(6) Use the ground wire to circle the clock area, the clock line should be as short as possible.
(7) I / O driver circuit as close to the PCB edge, let it leave the PCB as soon as possible. The signal into the PCB to be filtered, the signal from the high noise area to be added to filter, while the string termination resistor approach to reduce the signal reflection.
(8) MCD useless end to connect high, or ground, or defined as the output, the integrated circuit on the side of the power to be connected, do not hang.
(9) Leave unused gate input terminal should not be left vacant, unused amplifier input terminal is grounded, negative input termination output.
(10) PCB try to use the 45-fold line instead of 90 fold wiring in order to reduce the launch of high-frequency signals and coupling.
(11) PCB by frequency and current switching characteristics of zoning, noise components and non-noise components to be further away from some.
(12) Single-sided and double-sided use single-point power supply and single-point grounding, power lines, ground as thick as possible, the economy is affordable, then use multilayer to reduce the power of the inductances.
(13) Clock, bus, chip select signal away from the I / O lines and connectors.
(14) Analog voltage input line, the reference voltage should be as far as possible away from the digital circuit signal lines, especially the clock.
(15) For A / D devices, the digital part and the analog part should be more unified and do not cross.
(16) The clock line is perpendicular to the I / O line with less interference than the parallel I / O line and the clock element pin is far from the I / O line.
(17) Component pin as short as possible, decoupling capacitor pin as short as possible.
(18) The key lines should be as thick as possible and be protected on both sides. High-speed line should be short and straight.
(19) Noise-sensitive lines should not be parallel with high-current, high-speed switch lines.
(20) Do not route under quartz crystals and below noise-sensitive devices.
(21) Weak signal circuit, do not form a current loop around the low frequency circuit.
(22) The signal should not form a loop, which is as small as possible if unavoidable.
(23) One decoupling capacitor per integrated circuit. Add a small high-frequency bypass capacitor to the edge of each electrolytic capacitor.
(24) Use large capacity tantalum capacitor or condenser capacitor instead of electrolytic capacitor for charging and discharging the storage capacitor. When using tubular capacitors, the housing should be grounded.
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