Chiplet PCB Design: How Disaggregated AI Chips Change Substrate and Interconnect Requirements

Introduction: As Moore's Law decelerates, the semiconductor industry is shifting from massive monolithic dies to disaggregated chiplet architectures. By breaking down complex Systems-on-Chip (SoCs) into smaller, functionally optimized chiplets, hardware designers can achieve better yields, lower costs, and unparalleled scalability. However, this architectural revolution places unprecedented demands on the underlying advanced substrates and printed circuit boards (PCBs). This article explores how chiplet design transforms PCB routing, material selection, interconnect standards like UCIe, and the complex manufacturing processes required to support the next generation of AI hardware.

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1. Table of Contents

• The Evolution of Disaggregated AI Chips
• Understanding Chiplet Packaging Architectures
• The Impact of Chiplets on Advanced Substrates and PCBs
• Monolithic vs. Chiplet Substrate Requirements
• Key Interconnect Standards: UCIe and Beyond
• Manufacturing Challenges for Chiplet Substrates
• Frequently Asked Questions (FAQ)

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The Evolution of Disaggregated AI Chips

For decades, the semiconductor industry followed a straightforward path: shrink the transistors, pack more of them into a single monolithic silicon die, and reap the benefits of increased performance. However, in the era of generative AI, the reticle limit (the maximum physical size of a chip that can be printed using lithography, typically around 858 mm²) has become a hard barrier. When exploring what is an AI server, it becomes evident that the computational demands of large language models far exceed what a single reticle-limit chip can deliver.

To overcome this, engineers have adopted the chiplet model. A chiplet is a distinct, smaller die designed to perform a specific function (such as compute, memory, or I/O) that is combined with other chiplets within a single package. This "disaggregation" allows manufacturers to use different process nodes for different functions—for instance, using an expensive 3nm process for the core AI compute logic, while relying on a mature, cost-effective 12nm process for I/O controllers.

The recent NVIDIA Blackwell architecture is a prime example of this evolution. By utilizing two massive reticle-limit dies acting as a single GPU via an ultra-high-bandwidth interconnect, it perfectly illustrates how breaking the monolithic barrier changes not just the silicon, but the entire substrate and PCB ecosystem beneath it.

Understanding Chiplet Packaging Architectures

To understand the PCB implications, we must first look at how chiplets are packaged together. Unlike traditional chips that connect directly to a standard organic PCB, chiplets require an intermediate layer known as an advanced substrate or interposer to handle the extreme density of die-to-die (D2D) connections.

Here is a structural comparison of how these architectures differ at the physical level:

Monolithic SoC Architecture            Chiplet Architecture (2.5D/3D Integration)

+--------------------------+           +--------+  +--------+  +--------+
|                          |           |        |  |   AI   |  |        |
|    Single Large Die      |           | HBM3E  |  | Compute|  | HBM3E  |
|      (CPU/GPU/SoC)       |           |        |  | Chiplet|  |        |
|                          |           +--------+  +--------+  +--------+
+--------------------------+           ==================================
 ||||||||||||||||||||||||||               (Silicon Interposer / Bridge)
 ==========================            ==================================
   (Standard Organic PCB)                 (Advanced IC Substrate / PCB)
 ||||||||||||||||||||||||||            ||||||||||||||||||||||||||||||||||
 ==========================            ==================================
     (Motherboard / BGA)                       (Motherboard / OAM)

Advanced packaging technologies, such as CoWoS packaging (Chip-on-Wafer-on-Substrate), utilize a silicon interposer to connect multiple chiplets side-by-side (2.5D) before attaching them to the organic substrate. This shifts the burden of ultra-fine trace routing from the main PCB to the interposer and the IC substrate, fundamentally altering the PCB designer's role.

The Impact of Chiplets on Advanced Substrates and PCBs

The transition to chiplet design introduces a cascading effect on PCB engineering. When designing the underlying boards, whether they are standard form factor PCIe cards or specialized OAM modules, engineers must address several critical factors.

1. Explosive Growth in Pin Density and Bump Pitch Shrinkage

Traditional monolithic chips interface with PCBs using solder bumps with a pitch of around 150 μm to 200 μm. In a chiplet environment, the communication between the chiplet package and the main board requires significantly more I/O pins to support massive bandwidth. Advanced IC substrates now feature bump pitches approaching 50 μm to 130 μm. To fan out these signals to the main PCB, the board must feature High-Density Interconnect (HDI) structures, utilizing microvias, blind/buried vias, and any-layer via technologies.

2. Signal Integrity and Dielectric Materials

Die-to-die communication within a chiplet package operates at extremely high speeds, often transferring terabytes of data per second. While the highest frequency signals remain within the package, the substrate and the main PCB must still handle ultra-fast external I/O protocols like PCIe Gen6 and 112G PAM4. This necessitates the use of ultra-low loss dielectric materials. The dissipation factor (D_f) and dielectric constant (D_k) of the substrate materials must be strictly controlled to minimize signal attenuation and phase shift. Engineers must carefully calculate characteristic impedance (Z₀ = √(L/C)) to avoid disastrous signal reflections.

3. Power Delivery Network (PDN) Complexity

Chiplets require highly localized and distinct power rails. An AI compute chiplet might operate at 0.7V with massive current spikes (up to 1000A), while an adjacent I/O chiplet requires a steady 1.2V. The substrate and PCB must feature a highly complex Power Delivery Network (PDN). This involves placing decoupling capacitors as close to the dies as possible, often utilizing deep trench capacitors within the silicon interposer or embedding capacitors directly within the layers of the PCB substrate to minimize parasitic inductance (L_parasitic) and reduce I²R losses (where P = I²R).

4. Thermal Expansion and Warpage

One of the most severe challenges in chiplet PCB design is thermal management. Different materials—silicon dies, organic substrates, and FR4/Megtron PCBs—have different Coefficients of Thermal Expansion (CTE). When an AI server heats up under load, these materials expand at different rates. If the CTE mismatch is too great, it induces sheer stress on the microbumps, leading to cracked solder joints and board warpage. Substrate manufacturers must use specialized core materials and symmetrical layer stackups to maintain coplanarity.

Monolithic vs. Chiplet Substrate Requirements

To clearly illustrate the paradigm shift, the following table compares the typical PCB and substrate requirements for a legacy monolithic GPU versus a modern chiplet-based AI accelerator.

Parameter	Traditional Monolithic Design	Modern Chiplet Design (Advanced Substrate)
Die-to-Substrate Bump Pitch	150 μm - 200 μm	50 μm - 130 μm
Line / Space (L/S) Resolution	15 μm / 15 μm	2 μm / 2 μm (Interposer) to 8 μm / 8 μm (Substrate)
Layer Count (Package Substrate)	4 to 8 Layers	14 to 20+ Layers (e.g., 6-2-6 or 8-2-8 build-up)
Main PCB Layer Count	12 to 16 Layers	24 to 30+ Layers (often Any-Layer HDI)
Via Technology	Standard Vias, Mechanically Drilled	Laser-drilled Microvias, Via-in-Pad, Stacked Vias
Dielectric Material	Standard FR4 or Mid-Loss	ABF (Ajinomoto Build-up Film), Ultra-Low Loss

Key Interconnect Standards: UCIe and Beyond

For chiplets from different manufacturers to communicate on the same substrate, standardized interconnects are required. While proprietary solutions like Apple's UltraFusion exist, the industry is rapidly coalescing around the Universal Chiplet Interconnect Express (UCIe) standard.

UCIe defines the physical layer, protocol stack, and software model for die-to-die interconnects. From a PCB and substrate design perspective, UCIe operates in two main modes:

1. Standard Packaging Mode: Designed for chiplets mounted on standard organic substrates with bump pitches around 100-130 μm. This allows for lower-cost chiplet integration using traditional PCB manufacturing techniques, tracing signals up to 25 mm across the organic board.
2. Advanced Packaging Mode: Designed for silicon interposers or silicon bridges (like Intel's EMIB), utilizing sub-50 μm bump pitches. This provides maximum bandwidth density but pushes the routing complexity entirely off the main PCB and into the advanced packaging layer.

Additionally, while chiplets handle internal data, the assembled package must still communicate with other GPUs in the server rack. This requires external high-speed routing protocols. For more details on external routing, read our deep dive on what NVLink is and how it shapes PCB routing, as well as our comprehensive AI accelerator PCB design guide.

Manufacturing Challenges for Chiplet Substrates

Manufacturing the substrates that host chiplets bridges the gap between traditional PCB fabrication and semiconductor foundry processes. Traditional subtractive etching—where copper is etched away to leave traces—cannot achieve the ultra-fine Line/Space (L/S) requirements of chiplet substrates.

Instead, substrate manufacturers must utilize the mSAP (modified Semi-Additive Process). In mSAP, a very thin seed layer of copper is deposited, a photoresist is applied and developed to expose the trace patterns, and then copper is electrolytically plated up to the desired thickness. The resist is then stripped, and a quick flash etch removes the thin seed layer. This allows for near-vertical sidewalls on the copper traces, essential for maintaining impedance control at 8 μm / 8 μm L/S rules.

Furthermore, the use of ABF (Ajinomoto Build-up Film) is mandatory for these advanced substrates. ABF is a resin film that acts as the dielectric between routing layers. It supports extreme microvia laser drilling and provides the precise D_k and D_f properties required for high-speed chiplet communication.

Frequently Asked Questions (FAQ)

Q: What is the difference between a PCB and an IC Substrate?
A: While both serve as platforms for electronic components, an IC substrate is much smaller, features significantly finer trace widths (under 10 μm), uses ABF dielectrics, and acts as the direct interface for naked silicon dies (chiplets). The PCB is the larger motherboard that hosts the packaged IC substrate, utilizing standard FR4 or high-speed laminates with wider traces.

Q: Why can't we just route chiplet connections on a standard PCB?
A: The pin density of a chiplet requires bump pitches as small as 50 μm. Traditional PCBs simply cannot be manufactured with the trace widths and microvia sizes needed to fan out thousands of connections in such a small area without causing massive signal crosstalk and routing congestion.

Q: How does chiplet design affect power dissipation on the PCB?
A: Chiplet packages concentrate immense computational power in a small footprint, creating extreme thermal density. The main PCB must be designed with extensive thermal vias, heavy copper planes (often 2 oz or more), and sometimes embedded copper coins to draw heat away from the package and into the server's liquid cooling cold plates.

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