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How to use the IBIS model for signal integrity analysis

Posted:02:30 PM November 12, 2018 writer: G

1. Principles of Signal Integrity Analysis

Although various EDA tools implement different methods for signal integrity analysis, the basic principles are consistent. The circuit is composed of devices connected by wires. The basic unit of signal integrity analysis is the wiring network connecting several devices.

The I/O characteristics of the legs connected to each network are directly described by the IBIS model of the corresponding device (passive devices can also use the SPICE model), and the interconnecting wires between the devices are equivalent to the transmission line model. The specific parameters of the transmission line can be calculated according to the known parameters such as the thickness of the PCB board, the material, the number of layers, the line width and the spacing of the wiring, and the parasitic parameters such as parasitic capacitance, resistance, inductance, etc. caused by the cross-coupling of the wires between the networks. It can also be calculated. In this way, in the whole process of signal transmission, the main influencing factors from the source to the destination are included, and then according to the corresponding circuit theory, the signals can be accurately calculated in the transmission process. Kind of change.

2. Application of Signal Integrity Analysis

2.1 Signal Delay Analysis

Some high-speed digital circuits, such as memory interfaces, require that the clock phase deviation of each memory chip should not be too large, otherwise it may cause read and write errors, which requires that the clock delay from the clock generator to the receiving end of each chip due to PCB wiring is roughly equal. With the signal integrity analysis tool, it is easy to simulate the time delay of the clock reaching each chip, so as to adjust the corresponding layout and routing to meet the predetermined requirements.

2.2 Signal Distortion Analysis

The signal waveform can be used to visually observe the distortion of the signal during transmission, including overshoot, undershoot, and ringing. The IBIS model provides dynamic parameters of the circuit, so it can simulate the entire process of pulse transmission. Comparing the changes of the signal waveform before and after transmission, you can know whether the circuit design can meet the requirements. If it is not satisfied, you can make corresponding modifications.

2.3 Signal crosstalk analysis

Crosstalk refers to the interaction between two different electrical performance networks. The crosstalk is called Aggressor, and the interference is called Victim. Usually, a network is both Aggressor and Victim. Severe crosstalk can result in increased signal delay and increased waveform distortion. Crosstalk is one of the most difficult problems in circuit design because it is difficult to determine whether it is caused by crosstalk or other factors during the final debugging of the circuit. The best way to solve this problem at present is to simulate in the circuit design process, pre-select to avoid various problems that may be caused by crosstalk.

3. Signal Integrity Analysis Application Example

The following is an example of impedance matching to illustrate how to perform signal integrity analysis. The analysis tool uses Cadence's Signoise (other PCB design software has similar tools, such as PADS's Linesim and Boardsim, Protel's Signal Integrity Tools, etc.).

Impedance matching is a problem often encountered in circuit design. When the impedance of the load is not equal to the impedance of the driving source, the signal is reflected back and forth between the source and the destination multiple times, resulting in overshoot, ringing, etc., which deteriorates the signal quality. The purpose of impedance matching is to pass Terminate the appropriate resistor so that the impedance of the source and destination are approximately equal.

The example circuit is simple. A 74LS245 is used as a driving source to drive a 74LS245 load, and a resistor R is connected in the middle as an impedance matching resistor. The excitation signal is a 50MHz square wave with a 50% duty cycle.

Before the simulation, the device is first assigned an IBIS model, which is usually provided by the chip supplier, or can be modeled in Signoise's own model simulation library; then the excitation signal is set to a 50% square wave with a 50% duty cycle. This allows for simulation analysis. The wiring line width of the PCB board is 6 mil (mil: one thousandth of an inch). In order to highlight the transmission line effect, the length of the trace is extended to 5 inches. By changing the value of the impedance matching resistor R, a set of signals of the driving end and the load end can be obtained. curve.

It can be seen from the above curves that the change in matching resistance has a great influence on the signal quality. When the resistance value is small, the signal has a large oscillation. When the resistance value is too large, the signal rises slowly and the delay time becomes longer. When R=33Ω, the signal rises fast and does not oscillate, and the signal quality is the best, so the impedance matching resistor should be taken as 33Ω. It can be seen that signal integrity analysis can help us to find out the problems in circuit design early, and can modify the circuit parameters according to the simulation results to meet the predetermined requirements.

Now, under the design of the circuit board, it is developing in the direction of high density, high speed, miniaturization and low cost. Due to the fierce competition in the market, the technology is constantly updated, the design cycle is shorter and shorter, and the traditional design is verified after design. The method has been unable to adapt to this development trend. In foreign countries, design reuse, parallel design, and signal integrity verification have become the three requirements that designers admire. However, in China, due to various technical and financial constraints, it has not yet been widely applied. Therefore, it is urgent to learn and improve conditions to improve our design level and enhance the competitiveness of our products.

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