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PCB Design Preparation

writer: G May 31, 2019

Preparation before design

1. Accurate schematic diagram.

Includes complete schematic and netlist, formal BOM with component code. The PCB package for all devices in the schematic (for components not included in the package library, the hardware engineer should provide a datasheet or object and specify the order in which the pins are defined).

2. Provide PCB layout or important unit, core circuit placement position, mounting hole position, components that need to be restricted, and prohibited areas.

Design Flow

1. PCB documentation specification

File naming rules: Use the numbering method to control the version of the PCB file. The file name is composed of: project code - board name - version number - date.


Project code: Internal number is used for different project projects.

Board name: Simple explanation in English. For example, the baseboard – mainboard, panel – panel, etc.

The version number is unified by two, namely V10, V11, V30.... If there is a change in the schematic, the version upgrade changes the first digit, such as V10-V20; if it is only the layout change, the version upgrade changes the second digit, that is, V10-V11 and so on.

Date: Contains the year, month, and day in the format 20100108.

The entire code can only contain numbers and letters, connected by a dash.

2. Determine the package of the component

Open the netlist and browse through all the packages to ensure that all components are packaged correctly, especially the package size, pin order, aperture size and hole type and electrical properties (layer 25) must match the specifications on the datasheet , and the pad pins should be considered a little larger than the given size of the datasheet.

The package library and BOM of the component should be managed and maintained by a dedicated person to ensure uniform version.

3. Create a PCB frame

According to the customer's needs, determine the size of the frame and the location of the interface, as well as the installation holes, the forbidden area, the copper area and other related information.

4. Load the netlist

Load the netlist into the PCB and check the import report to ensure that all components are packaged correctly.

5. Stacking settings

Factors to consider when stacking settings:

1. Stable, low noise, low AC impedance PDS (Power Distribution System).

2. Transmission line structure requirements, microstrip line or strip line, whether there is a coating layer, etc.

3. Characteristic impedance requirements of the transmission line.

4. Crosstalk noise suppression.

5. Absorption and shielding of spatial electromagnetic interference.

6. The structure is symmetrical to prevent deformation.

The wiring density determines the number of signal layers. The place with the highest wiring density is usually around the CPU. The number of pins on the CPU determines the number of signal layers that need to be used.

The thickness of the copper and the thickness of the dielectric layer are determined by the impedance control. Therefore, it is necessary to calculate the stacking parameters of 50 OHM single-ended impedance and 100 OHM differential impedance using simulation software (such as hyperlynx or SI9000) to determine the stack design.

Power and ground plane design: Try to design the power supply and the ground plane adjacent, and the thinner the dielectric between the power supply and the ground layer, the better, which can provide a good distribution decoupling capacitor, which can greatly improve the system. Signal integrity and EMC form a stable, low noise and low AC impedance PDS. The ground plane should be placed on a layer directly adjacent to the PCB surface of the mounting component. The closer the ground plane is to the PCB main component surface (usually the surface layer), the lower the interconnect inductance will fall.

The laminate design also needs to consider the warpage of the layer, that is, the laminate is designed to be vertically symmetrical.

The general rules for high speed digital design are:

1. Number of power layers + number of layers = number of signal layers

2. The power and ground are designed in pairs as much as possible, and at least one pair is a “back to back” design.

3. The trace line should adopt the strip line structure as much as possible, and have better EMC shielding, and the key signal transmission should adopt the symmetrical strip line structure (the specific electromagnetic field distribution can be viewed by the 2D field solver, and the hyperlynx also has this function).

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