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What kind of PCB stacking strategy helps shield and suppress EMI?
Posted:02:51 PM July 19, 2018 writer: G

4-layer board

There are several potential problems with 4-layer board design. First, the conventional four-layer board with a thickness of 62 mil, even if the signal layer is on the outer layer, the power supply and the ground layer are in the inner layer, the distance between the power supply layer and the ground layer is still too large.

If the cost requirement is first, consider the following two alternatives to traditional 4-layer boards. Both of these solutions improve EMI suppression performance, but only for applications where the on-board component density is low enough and there is sufficient area around the component to place the required copper layer on the power supply.

The first is the preferred solution. The outer layers of the PCB are all ground layers, and the middle two layers are signal/power layers. The power supply on the signal layer is routed with a wide line, which allows the path impedance of the supply current to be low and the impedance of the signal microstrip path to be low. From the perspective of EMI control, this is the best 4-layer PCB structure available. The outer layer of the second scheme takes the power and the ground, and the middle two layers take the signal. Compared with the traditional 4-layer board, the improvement is smaller, and the interlayer resistance is as poor as the traditional 4-layer board.

If you want to control the trace impedance, the above stacking scheme must be very careful to place the traces under the power and ground copper islands. In addition, the copper or copper islands on the ground should be interconnected as much as possible to ensure DC and low frequency connectivity.


6-layer board

If the density of the components on the 4-layer board is relatively large, it is preferable to use a 6-layer board. However, some laminate solutions in the 6-layer board design do not have a good shielding effect on the electromagnetic field, and have little effect on the reduction of the power bus bus transient signal. Two examples are discussed below.

In the first case, the power and ground were placed on the 2nd and 5th layers respectively. Due to the high impedance of the copper of the power supply, it is very disadvantageous for controlling the common mode EMI radiation. However, from the point of view of signal impedance control, this method is very correct.

In the second example, the power supply and the ground are placed on the 3rd and 4th layers respectively. This design solves the problem of the copper-clad impedance of the power supply. Due to the poor electromagnetic shielding performance of the first layer and the sixth layer, the differential mode EMI is increased. This design can solve the differential mode EMI problem if the number of signal lines on the two outer layers is the least and the trace length is short (shorter than the 1/20 of the highest harmonic wavelength of the signal). The suppression of differential mode EMI is particularly good when copper is filled with no components and no trace areas on the outer layer and the copper area is grounded (interval every 1/20 wavelength). As mentioned earlier, the copper area is connected to the internal ground plane at multiple points.

The general-purpose high-performance 6-layer board design generally lays the first and sixth layers as the ground layer, and the third and fourth layers take the power and ground. Since there are two layers of the centered double microstrip signal line layer between the power supply layer and the ground layer, the EMI suppression capability is excellent. The disadvantage of this design is that the trace layer has only two layers. As mentioned earlier, if the outer traces are short and copper is laid in the no trace area, the same stack can be achieved with a conventional 6-layer board.

Another 6-layer board layout is signal, ground, signal, power, ground, and signal, which enables the environment required for advanced signal integrity design. The signal layer is adjacent to the ground layer, and the power layer and the ground layer are paired. Obviously, the downside is that the stacking of layers is unbalanced.

This usually causes troubles in manufacturing. The solution to the problem is to fill all the blank areas of the third layer with copper. If the copper layer density of the third layer is close to the power layer or the ground layer after copper filling, the board can not be strictly regarded as a structurally balanced circuit board. . The copper filled area must be connected to power or ground. The distance between the connecting vias is still 1/20 wavelength, and it is not necessary to connect everywhere, but ideally it should be connected.


10-layer board

Since the insulating isolation layer between the multilayer boards is very thin, the impedance between the 10 or 12 layer circuit board layers and the layers is very low, and excellent signal integrity is completely expected as long as the layering and stacking are not problematic. It is difficult to process 12-layer boards at a thickness of 62 mils, and there are not many manufacturers that can process 12-layer boards.

Since the signal layer and the loop layer are always separated by an insulating layer, the scheme of distributing the middle 6 layers to walk the signal line in the 10-layer board design is not optimal. In addition, it is important to have the signal layer adjacent to the loop layer, that is, the board layout is signal, ground, signal, signal, power, ground, signal, signal, ground, and signal.

This design provides a good path for signal current and its loop current. The proper routing strategy is that the first layer is routed along the X direction, the third layer is routed along the Y direction, the fourth layer is routed along the X direction, and so on. Intuitively looking at the traces, the first layer 1 and the third layer are a pair of layered combinations, the fourth layer and the seventh layer are a pair of layered combinations, and the eighth layer and the tenth layer are the last pair of layered combinations. When it is necessary to change the direction of the trace, the signal line on the first layer should be changed direction by "via" to the third layer. In fact, it may not always be possible to do so, but as a design concept, try to comply as much as possible.

Similarly, when the direction of the signal is changed, it should pass through the vias from the 8th and 10th layers or from the 4th to the 7th. This routing ensures that the coupling between the forward path and the loop of the signal is tightest. For example, if the signal is routed on the first layer and the loop is on the second layer and only on the second layer, then the signal on the first layer is transferred to the third layer even by "via". The loop is still on the second layer, maintaining low inductance, large capacitance characteristics and good electromagnetic shielding performance.

What if the actual route is not the case? For example, the signal line on the first layer passes through the via hole to the 10th layer. At this time, the loop signal has to find the ground plane from the 9th layer, and the loop current needs to find the nearest ground via (such as the grounding pin of the component such as resistor or capacitor). . If there is such a via in the vicinity, it is really lucky. If no such via is available, the inductance will increase, the capacitance will decrease, and EMI will increase.

When the signal line must leave the current pair of wiring layers through the via to other wiring layers, the ground via should be placed near the via, so that the loop signal can be smoothly returned to the proper ground plane. For Layer 4 and Layer 7 layered combinations, the signal loop will be returned from the power or ground plane (ie, Layer 5 or Layer 6) because the capacitive coupling between the power and ground planes is good and the signal is easily transmitted. .

Multi-power layer design

If the two power planes of the same voltage source need to output a large current, the board should be laid into two sets of power and ground planes. In this case, an insulating layer is placed between each pair of the power supply layer and the ground layer. This gives us two pairs of equal-impedance power buss that we want to divide the current. If the stack of power planes causes unequal impedances, the shunt is not uniform, the transient voltage will be much larger, and EMI will increase dramatically.

If there are multiple supply voltages with different values on the board, multiple power planes are required accordingly. It is important to remember to create separate pairs of power and ground planes for different power supplies. In both cases, when determining the location of the paired power and ground planes on the board, remember the manufacturer's requirements for the balanced structure.

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