Listed below are some of the issues that have received much attention.
1. The impact of routing topology on signal integrity
Signal integrity issues can occur when signals are transmitted along a transmission line on a high speed PCB. STMicroelectronics user tongyang asked: For a group of buses (address, data, command) to drive up to 4, 5 devices (FLASH, SDRAM, etc.), in the PCB wiring, the bus arrives at each device in turn, such as Connected to SDRAM, then to FLASH... or the bus is star-shaped, that is, separated from somewhere and connected to each device. Which of the two methods is better in signal integrity?
The influence of the wiring topology on signal integrity is mainly reflected in the inconsistency of the signal arrival times at each node, and the time at which the reflected signal arrives at a certain node is also inconsistent, resulting in deterioration of signal quality. In general, the star topology can control the signal transmission and reflection delay by controlling several branches of the same length to achieve better signal quality. Between the use of the topology, the signal topology node conditions, the actual working principle and the wiring difficulty should be considered. Different Buffers have inconsistent effects on the reflection of signals. Therefore, the star topology does not solve the delay of connecting the above data address bus to FLASH and SDRAM, so that the quality of the signal cannot be ensured. On the other hand, the high-speed signal is generally Communication between DSP and SDRAM, FLASH loading rate is not high, so in high-speed simulation, as long as the waveform of the node where the actual high-speed signal works effectively, without paying attention to the waveform at FLASH; star topology comparison daisy chain and other topologies In other words, wiring is difficult, especially when a large number of data address signals are in a star topology.
2. The effect of pads on high speed signals
In the PCB, from the design point of view, a via is mainly composed of two parts: the middle hole and the pad around the hole. An engineer named fulonm asked the guest pad how it affects the high-speed signal. In this regard, Li Baolong said: The pad has an impact on the high-speed signal, which affects the influence of the package of the device on the device. Detailed analysis, after the signal comes out of the IC, through the bonding wires, pins, package casing, pads, solder to the transmission line, all the joints in this process will affect the signal quality. However, in actual analysis, it is difficult to give the specific parameters of the pad, solder and pin. Therefore, they are generally summarized by the parameters of the package in the IBIS model. Of course, such an analysis can be received at a lower frequency, but a higher precision simulation for a higher frequency signal is not accurate enough. A current trend is to describe the Buffer characteristics using the V-I and V-T curves of IBIS and the package parameters using the SPICE model.
3. How to suppress electromagnetic interference
PCB is the source of electromagnetic interference (EMI), so PCB design is directly related to the electromagnetic compatibility (EMC) of electronic products. Focusing on EMC/EMI in high-speed PCB design will help shorten product development cycles and speed time-to-market. Therefore, many engineers are very concerned about the problem of suppressing electromagnetic interference in this forum. For example, experts said that the harmonics of the clock signal were found to be very serious in the EMC test. Is it necessary to specially handle the power supply pin of the IC that uses the clock signal? Currently, only the decoupling capacitor is connected to the power supply pin. . In the PCB design, what aspects should be paid attention to to suppress electromagnetic radiation? In this regard, Li Baolong pointed out that the three elements of EMC are radiation sources, transmission routes and victims. The propagation route is divided into space radiation propagation and cable conduction. So to suppress harmonics, first look at the way it spreads. Power supply decoupling is to address conduction propagation and, in addition, the necessary matching and shielding is also required.
Some experts pointed out that filtering is a good way to solve the problem of EMC radiation through conduction. In addition, it can also be considered from the source of interference and the victim. For interference sources, try to use an oscilloscope to check if the rising edge of the signal is too fast, there is reflection or Overshoot, undershoot or ringing. If there is, you can consider matching; also try to avoid the 50% duty cycle signal, because this signal is not even Subharmonics, more high frequency components. In terms of victims, measures such as land acquisition can be considered.
4. Is the RF wiring selected for via or bend wiring?
There are few netizens asking questions about high-speed analog circuit design. For example, one of the netizens asked: In the high-speed PCB, too, the large return path can be reduced, but some people say that they would rather not bend it, so how should they choose?
Analysis of the return path of the RF circuit is not the same as signal return in high speed digital circuits. What they have in common is the distributed parameter circuit, which is the characteristic of the calculation circuit using Maxwell equation. However, the RF circuit is an analog circuit. There are two variables, voltage V=V(t) and current I=I(t), which need to be controlled. The digital circuit only pays attention to the change of the signal voltage V=V(t). Therefore, in the RF wiring, in addition to considering the signal reflow, it is also necessary to consider the influence of the wiring on the current. That is, the bend wiring and vias have no effect on the signal current. In addition, most RF boards are single-sided or double-sided PCBs, and there is no complete planar layer. The return path is distributed around the signal and the power supply. When simulating, it needs to be analyzed by 3D field extraction tool. The reflow of vias requires specific analysis; high-speed digital circuit analysis typically only processes multi-layer PCBs with complete planar layers, using 2D field extraction analysis, only considering signal reflow in adjacent planes, vias only as a lumped parameter RLC deal with.
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