148 Checklist for PCB Design, Part 2

writer: G December 27, 2017

76. Close to the connector panel with cloth 10 ~ 20mm protective ground, and with double staggered hole to connect the layers?

77. The distance between the power cord and other signal lines to meet the safety requirements?

78. Metal shell devices and cooling devices, there should be no possible short circuit traces, copper and vias

79. Mounting screws or washer should not have around the wiring may cause short circuit, copper and vias

80. Design requirements in the reserved location for alignment

81. Non-metallic hole inside the line from the circuit and the copper foil spacing should be greater than 0.5mm (20mil), the outer 0.3mm (12mil)

82. Copper and wire to the edge of the board is recommended for more than 2mm minimum 0.5mm

83. The inner layer of copper to the edge of the plate 1 ~ 2 mm, a minimum of 0.5mm

84. For two pad mounted CHIP components (0805 and below), such as resistors and capacitors, the traces connected to their pads are preferably symmetrically drawn from the center of the pad and printed with the pads The lines must have the same width, for the line width of less than 0.3mm (12mil) leads may not consider this article

85. With the wider printed wiring connection pad, the middle of the best through a narrow line transition? (0805 and below package)

86. The circuit should try to lead from both ends of the pad of SOIC, PLCC, QFP, SOT and so on

87. Is the device's bit number missing, the location can correctly identify the device?

88. The device number is in line with company standards

89. Confirm the device pinout order, the first leg of the flag, the polarity of the device logo, the correct direction of the connector identification

90. Motherboard and daughter card board direction mark whether the corresponding

91. Is the backplane the slot name, slot number, port name, and sheath direction correctly?

92. confirm the design requirements of the silk screen to add the correct

93. Confirm that you have placed anti-static and radio frequency board identification (RF board use)

94. Verify that the PCB code is correct and in accordance with the company's specifications

95. Confirm that the PCB coding position and level of the veneer are correct (should be in the upper left of the A side

96. Confirm that the backplane's PCB coding position and level is correct (should be at the top right of B.)

97. confirm the bar code laser printing white silk screen marking area

98. Verify that there is no wire below the barcode bar and vias above 0.5mm

99. confirm the bar code white screen outside the area of 20mm can not have a height of more than 25mm components

100. Reflow surface, the vias can not be designed on the pad. (Normally fenestrated vias and pads should be spaced more than 0.5mm (20mils) apart), and the green-capped vias and pads should be spaced more than 0.1mm (4mils) by opening the Same Net DRC, checking DRC, Then shut down Same Net DRC)

101. The arrangement of vias should not be too dense, to avoid causing power, large-scale fracture of the ground plane

102. Drilled hole diameter is best not less than the thickness of 1/10

103. device placement rate is 100%, Plot rate is 100% (100% did not meet the need to note)

104. Dangling line has been adjusted to a minimum, for the retention of the Dangling line has made one by one confirmed;

105. Craft Division feedback technology problems have been carefully checked

106. For Top and Bottom large area copper foil, if there is no special requirement, apply grid copper [Inclined grid for boards, orthogonal grid for back boards, line width 0.3mm (12 mil), pitch 0.5mm 20mil)]

107. Large area of the copper foil pad components, should be designed into flower pads, in order to avoid Weld; current requirements, then consider widening the flower pad ribs, and then consider the full connection

108. Large copper cloth, you should try to avoid the emergence of dead copper without network connection (island)

109. Large copper foil also need to pay attention to whether there is illegal connection, unreported DRC

110. A variety of power, the test point is sufficient (at least one test point per 2A current)

111. Verify that no networks with test points are validated for streamlining

112. Verify that the test point is not set on the plug-in that is not installed during production

113. Test Via, Test Pin has been Fix (for testing the needle bed does not change the board)

114. Test via and Test pin Spacing Rule should be set to the recommended distance, check the DRC, if there is still DRC, and then set the minimum distance to check the DRC

115. Open the constraint set to open the state, update the DRC to see if DRC not allowed to error

116. Confirm that the DRC has been adjusted to a minimum, and that one can not confirm the elimination of the DRC;

117. Verify that there is an optical alignment symbol for the PCB surface on which the component is mounted

118. Confirm that the optical positioning symbol is not pressed (screen printing and copper foil routing)

119. Optical positioning point background to be the same, confirm the whole board using the optical point of the center from the edge ≥ 5mm

120. Verify that the entire board's optical positioning reference symbol has been assigned a coordinate value (it is recommended to place the optical positioning reference symbol in the form of a device) and is an integer value in millimeters.

121. ICs with <0.5mm center pin pitch and BGA devices with a center pitch of less than 0.8mm (31 mil) should be provided with optical alignment points near the diagonal of the component

122. To confirm whether there are special requirements of the types of pads are correct to open the window (with particular attention to the hardware design requirements)

123. BGA under the hole is processed into cap plug holes

124. In addition to testing the vias outside the hole has been made small window or cap hole

125. Optical positioning of the window to avoid the exposed copper and exposed lines

126. Power chip, crystal and other copper heat sink or ground shielding devices, there is copper and the correct window. Devices that are fixed by solder should have a large area of green solder to block solder diffusion

127. Notes PCB thickness, layer number, screen color, warp, and other technical instructions are correct

128. Stacking layer name, stacking order, the thickness of the media, the thickness of the copper foil is correct; whether the requirements for impedance control, the description is accurate. The layer name of the stacked drawing is the same as the name of the painted file

129. Turn off Repeat code in the setting table, drilling accuracy should be set to 2-5

130. hole table and drilling files are up-to-date (change holes, you must regenerate)

131. Hole table in the presence of abnormal aperture, the pressure is correct pore size; aperture tolerance is marked correctly

132. Was the hole in the main hole listed separately and labeled "filled vias"

133. Gerber file output as far as possible using RS274X format, and accuracy should be set to 5: 5

134 art_aper.txt whether the latest (274X may not need)

135. Output light file log file whether there is an exception report

136. Negative slice edges and islands to confirm

137. Use the paint inspection tool to check if the paint file matches the PCB (use the alignment tool to change the plate)

138. PCB File: Product Model_ Specification_ Veneer Code_ Version Number .brd

139. Backing board design documents: Product Model_ Specifications _ veneer code _ version number-CB [-T / B] .brd

140. PCB processing documents: PCB coding. Zip (including all layers of light painting files, aperture table, drilling files and ncdrill.log; puzzle also need to have the craft puzzle file *. Dxf)

141. Process Design Document: Product Model_ Specs _ Board Code _ Version -GY.doc

142. SMT Coordinate Documents: Product Model_ Specification_ veneer code_ version number-SMT.txt

143. PCB Board Structure File: Product Model_Specification_Single Board Code_Version_MCAD.zip (contains the .DXF and .EMN files provided by the structural engineer)

144. Test Files: Product Model_Specification_Single Code_ Version Number -TEST.ZIP (a coordinate file containing testprep.log and untest.lst or * .drl test points)

145. Filing drawing documents: Product Model Specification - veneer name - version number .pdf

146. Confirm the cover, the home page information is correct

147. Confirm that the drawing number (corresponding to the order of PCB layers) is correct

148. Verify that the PCB code on the drawing box is correct


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