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Source synchronization timing relationship and simulation examples
Posted:04:55 PM August 30, 2018 writer: G

Settling time: Tvb_min+(Tflt_clk_min-Tflt_data_settle_delay_max)-Tsetup-Tmargin>0

Hold time: Tva_min+(Tflt_data_switch_delay min-Tflt_clk _max)-Thold-Tmargin>0

Tvb is the setup time of the drive end, indicating how long the drive end data is valid before the clock is valid; Tva is the hold time of the transmit end, indicating that the drive end data remains valid after the clock is valid; other parameters have the same meaning. The source synchronization timing analysis and simulation process are introduced below by taking the TBI interface which is very common in communication circuits as an example. The TBI interface mainly includes a transmission clock and 10 bits of transmission data, two reception clocks, and 10 bits of reception data. RBC0 and RBC1 are two receiving clocks. In Gigabit Ethernet, the two clock frequencies are 62.5MHz with a phase difference of 180°. The rising edges of the two clocks are used to latch data. According to the timing parameters of the data sheet, substituting the above formula can be obtained:

2.5+ Tflt_clk _min-Tflt_data__settle_delay_max -1-Tmargin>0

1.5+ Tflt_data__switch_delay min-Tflt_clk _max -0.5-Tmargin>0

Model the following analysis: Assume that the flight time of the clock and data signal lines are strictly equal, that is, the clock and data are perfectly matched, and then analyze the effects of their mismatch. The above formula becomes

1.5-Tmargin>0

1-Tmargin>0

It can be seen that there is a large margin in both the setup time and the hold time. After simulation, it is found that the data and the clock match exactly the same length (taking 0.02 ns as an example), there is still a difference of 0.3 ns, ie,

Tflt_clk_min-Tflt_data_settle_delay_max <0.3< p="">

Tflt_data_switch_delay min-Tflt_clk_max <0.3< p="">

Take Tmargin=0.5ns to get the clock and data match to 0.2ns, that is, the data and clock length should not match 0.2ns.

In the actual simulation, the signal integrity of the clock and data is first analyzed and simulated, and the better received waveform is obtained by proper termination matching.

In common clock synchronization, the transmission and reception of data must be completed in one clock cycle. At the same time, the delay of the device and the delay of the PCB trace also limit the maximum theoretical operating frequency of the common clock bus. Therefore, the common clock synchronization is generally used for transmission rates below 200 MHz to 300 MHz. Transmissions above this rate should generally incorporate source synchronization techniques. The source synchronous technology works under the relative clock system, and uses data and clock to transmit in parallel. The transmission rate is mainly determined by the time difference between the data and the clock signal, so that the system can achieve a higher transmission rate. Through signal integrity analysis, timing analysis and simulation of the broadband Ethernet switch host and daughter card board, the author greatly shortens the product design cycle, and effectively solves the signal integrity and timing in high-speed design through analysis and simulation. The problem fully guarantees the quality of the design and the design speed, and truly achieves one pass of the PCB board. The motherboard and daughter card board have been debugged and successfully.

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