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Singnal Integrity terminology (12-22)
Posted:10:29 AM October 31, 2018 writer: G

The pin-to-pin delay refers to the time between the change of the state of the drive to the change of the state of the receiver. These changes typically occur at 50% of a given voltage. The minimum delay occurs when the output first crosses a given threshold (threshold), and the maximum delay occurs when the output last crosses the voltage threshold (threshold). All of these situations.

13. What is skew?

The skew of the signal is the time offset between the different receivers arriving at the same network. The skew is also used for the time offset of the clock and data reached on the logic gate.

14. What is the slope (slew rate)?

Slew rate is the edge slope (the ratio of the time change associated with the voltage of a signal). The I/O specification (eg PCI) state is between two voltages, which is the slew rate, which is measurable.

15. What is a quiescent line?

It does not switch during the current clock cycle. Also known as the "stuck-at" line or the static line. Crosstalk can cause a static line to toggle during a clock cycle.

16. What is a false clocking?

A fake clock means that the clock unconsciously changes state beyond the threshold (sometimes between VIL or VIH). Usually caused by excessive undershoot or crostalk.

17. What is IBIS?

IBIS is an EIA/ANSI standard that describes an input/output (I/O). It includes the DC (V/I) characteristic curve and also includes the transient (V/T) characteristic curve curves as tables of points. HyperLynx's Web site has a home page that connects to IBIS, as well as a number of vendors' IBIS model pages.

18. What is the high and low level switching threshold of the IC?

The high and low switching thresholds of an IC refer to the voltage values required for a signal to transition from one state to another. When damping occurs, the signal level may exceed the switching threshold of the IC input pin, which turns the IC input signal into an indeterminate state, which can cause clock errors or incorrect reception of data.

19. What is the ground plane bounce noise and return noise?

When there is a large current surge in the circuit, it will cause ground plane bounce noise (referred to as ground bounce). If the output of a large number of chips is turned on at the same time, there will be a large transient current flowing through the power plane of the chip and the board. The inductance and resistance of the chip package and the power plane can cause power supply noise, which will cause voltage fluctuations and changes on the true ground plane (0V), which will affect the operation of other components. An increase in the load capacitance, a decrease in the load resistance, an increase in the ground inductance, and an increase in the number of switching devices at the same time may result in an increase in the ground bounce.

Due to the division of the geoelectric plane (including power and ground), for example, the ground layer is divided into digital ground, analog ground, shield ground, etc., when the digital signal goes to the analog ground area, ground plane return noise is generated. The same power layer may be split into 2.5V, 3.3V, 5V, etc. Therefore, in multi-voltage PCB design, the rebound noise and return noise of the geoelectric plane need special attention.

20. Definition of high frequency circuit

In digital circuits, whether or not a high frequency circuit depends on the rising and falling edges of the signal, not the frequency of the signal.

F=1/(Tr*л), Tr is the rise/fall delay time. When F>100MH (Tr<3.183ns), it should be considered according to the high frequency circuit. The following conditions must be designed according to the high frequency rule: < span="">

l The system clock exceeds 50 Hz.

l Use devices with rise/fall times less than 5ns

l Digital / analog hybrid circuit

The high-frequency circuit depends on the rising edge and falling edge of the signal, not the frequency of the signal, but it is not the design of the high-frequency rule when Tr>100MHz, depending on the transmission medium. It is generally agreed that if the line propagation delay is greater than the rise time of the 1/2 digital signal drive, such signals are considered to be high speed signals and produce transmission line effects. The transmission of the signal occurs at the moment the signal state changes, such as the rise or fall time. The signal passes from the driver to the receiver for a fixed period of time. If the transmission time is less than 1/2 of the rise or fall time, the reflected signal from the receiver will reach the driver before the signal changes state. Conversely, the reflected signal will arrive at the drive after the signal changes state. If the reflected signal is strong, the superimposed waveform may change the logic state.

21. What is the long line?

Definition of Longitudinal Trace in High Speed Systems

It can be defined from both the frequency domain and the time domain:

1) Frequency domain definition

When the physical length of the line is comparable to the wavelength of the corresponding frequency (generally greater than 1/20 wavelength), such a trace is called an Electrically Long Trace, or a transmission line.

2) Time domain definition

When the propagation delay of the signal line is greater than 1/4 of the rise time of the signal, the signal line should be regarded as the transmission line.

22. What is a microstrip line and a strip line?

1) Microstrip line

There is only one reference plane. Some friends think that the microstrip line is the transmission line on the surface of the PCB. This view is not comprehensive. Imagine a situation where the first and second layers of a multilayer board are both signal layers and the third layer is ground plane, then the transmission lines on the first and second layers are called microstrip lines. The microstrip line on the second layer is also called an embedded microstrip. The impedance of the microstrip line is related to its line width, frequency, and its vertical distance from the reference plane.

2) Stripline

It is located between two reference planes, so it has two reference planes, and the calculation formula of the impedance is different from that of the microstrip line. Of course, the stripline must be located in the inner layer of the PCB.

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