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Signal Integrity Analysis of MCM High Speed ​​Circuit Layout Design

Posted:03:44 PM November 23, 2018 writer: G

With the development of integrated circuit process technology, the operation speed of multi-chip components is getting higher and higher, and the processing of high-speed signals has become the key to the success of MCM circuit design. When the rising or falling edge of the clock signal is small, the transmission line effect is caused, that is, signal integrity problems occur.

This design takes the detector circuit as an example, and elaborates the method of MCM layout design using signal integrity analysis tool. First, the package parts library is expanded to meet the needs of specific circuit layout design; then APD (Advanced Package Designer) software is used to directly call the part package symbols to complete the initial layout design of the circuit; finally, combined with reflection, delay and electromagnetic compatibility The signal integrity simulation analysis results are repeatedly adjusted. The improved circuit layout and wiring reduces the reflection of the signal. The relative delay of the input signal does not exceed 0.2 ns, and the electromagnetic interference phenomenon is also suppressed to meet the signal integrity requirements.

1.MCM layout and software implementation

As mentioned above, the implementation of MCM place and route includes circuit schematic generation, extended part library and final place and route completion and processing data file output. APD Layout includes Padstack (*.pad), Package Symbol (*.psm), Mechanical Symbol (*.bsm), Format Symbol (*.osm) and Shape Symbol (*.ssm), MCM layout design, All layouts must have the correct Library Packing. The MCM design software comes with a package library that often cannot meet the specific design requirements. Only after the part library is expanded can the parts be directly called for layout design and final process file output. First, use the Padstack Editor software to expand the parts library, then package the circuit, and export the electrical connection netlist file to the APD software through Concept HDL, and finally complete the circuit layout. Throughout the design, 16 Padstacks and 81 package symbols were defined, 251 calls to Padstack and 89 calls to the functional unit, which shared 251 component package symbol pins and 229 function unit pins.

It should be noted that, in the specific design, if you use Orcad to design the circuit, you must convert the file generated by Orcad into the mcm file of the APD software. However, since the converted mcm file has a problem similar to brd, the Concept HDL software is used to export the netlist file, and then the network cable topology is extracted for simulation. In order to reduce the simulation time, a sub-module simulation method is adopted.

2. Simulation analysis

IBIS model

Like other circuit analysis software, Spectra Quest must first provide accurate electrical models of circuit components in order to obtain accurate simulation results. The Spectra Quest software uses the IBIS model. The IBIS (Input/Output Buffer Information Specification) model uses I/V and V/T tables to describe the characteristics of I/O cells and pins. It is a fast and accurate I/O BUFFER based on V/I curve. Modular method. It provides a standard file format for recording parameters such as driver or receiver output impedance, rise/fall time, and input load, which are read by Spectra Quest. The IBIS model has the information needed for signal integrity analysis and is ideal for calculation and simulation of high frequency effects such as oscillation and crosstalk.

The Sigxplorer inside Spectra Quest accepts the IBIS model and then transforms it into a unique design modeling language DML to model complex I/O structures. Moreover, the Constraint Manager in Sigxplorer manages the parameters used in the simulation and embeds them into subsequent place and route constraints.

3. Reflection analysis

The reflection, that is, the echo on the transmission line, is caused by the discontinuity of the impedance. A mismatch between the source and load impedances causes reflections on the line, and the load reflects a portion of the voltage back to the source. If the load impedance is less than the source impedance, the reflected voltage is negative; otherwise, the reflected voltage is positive. Ideally, the output impedance, transmission line impedance, and load impedance are equal. At this point, the impedance of the transmission line is continuous and no reflection occurs. The amplitude of the reflected voltage signal is determined by the source reflection coefficient rS and the load reflection coefficient rL.

The key to solve the transmission line reflection is impedance control. Impedance matching can suppress transmission line reflection. There are four matching termination methods: parallel termination, Thevenin equivalent parallel termination, AC termination and series termination. Here, the Thevenin equivalent parallel termination method is used to control the input impedance of the detector circuit, and then the circuit topology is extracted to simulate the transmission characteristics of the circuit before and after the termination.

Before the termination, the waveform has distortion on the rising edge, which may cause misoperation. The matching termination effectively eliminates the distortion of the signal, and the monotonicity is very good, and the original signal is pulled up on the rising edge, and the level switching is advanced in advance, the steady state time of the signal is increased, and the rising edge of the signal is relatively stable. Although there is an overshoot in the high-level maintenance phase, it has no effect on the signal confirmation, and the signal quality is ideal. In addition, the length of the signal transmission line also has a certain influence on the reflection. The simulation found that when the transmission line is long, the predicted reflection phenomenon occurs; when the transmission line is short, the simulation waveform and the analysis result agree very well. Therefore, the wiring length is different and the processing method should be different. In general, trace lengths are less than 2 inches and are handled by LC circuits with lumped parameters; greater than 8 inches are treated with transmission line circuits with distributed parameters.

4. Delay analysis

As the operating frequency of the system increases, the routing delay can no longer be ignored when the rising or falling edge of the signal is steep. It plays a vital role in the establishment and maintenance of the signal, and may even affect the timing of the system, causing misoperations, so it must be considered. The MCM high-speed circuit design requires that the phase deviation of the memory chip should not be too large, so the wiring delay from the driver to the receiver should be approximately equal. The length of the signal line has a great influence on the transmission quality, which may cause the signal to be distorted during transmission. The signal transmission quality deteriorates as the line length increases. For long signal lines, the source or terminal matching method should be used to improve the transmission quality. The signal integrity simulation tool can be used to easily simulate the delay from the driver to each chip, and then adjust the layout and wiring according to the simulation results to meet the predetermined requirements.

Each signal of the detector should be kept at the same transmission delay as much as possible. This requires that the wiring be kept as long as possible. For weak differences, the wiring can be extended or shortened according to the simulation results. After the wiring is completed, the transmission delay of the input signal is simulated by Spectra Quest software. The specific parameters are shown in Table 2. It can be seen that the relative delay does not exceed 0.2 ns, and the simulation results are ideal.

5. EMI analysis

In addition to analyzing the reflection and delay of the signal in the time domain, EMI (electromagnetic interference) is also an important aspect of high-speed circuit design.

Electromagnetic interference, including excessive electromagnetic radiation and sensitivity to electromagnetic radiation, can cause electromagnetic interference effects if the operating frequency is too high, the signal changes too fast, or the layout and wiring are unreasonable. The EMI simulation is performed on the change of the wiring strategy and the increase of the detector circuit before and after the terminal matching. The noise generated by the signal continues from 0 to 2 GHz, the range is very wide, and the radiation intensity of each frequency is not the same. The radiation intensity of some frequencies exceeds the limit, that is, the electromagnetic interference of the signal at this frequency is beyond the reach of the system. To the extent that measures should be taken to reduce their radiation levels. Perform impedance control as described above and minimize the wiring length. It can be seen that the frequency wave exceeding the limit has fallen below the horizontal line, and the radiation intensity at each frequency point has decreased, and the entire radiation intensity has been reduced. This shows that for the transmission signal, changing the wiring length and adding an appropriate matching termination network not only improve the signal transmission characteristics, but also reduce the electromagnetic radiation intensity and improve the signal quality.


In the design of high-speed circuits, the signal integrity and EMI simulation analysis of the system functions are first performed using an accurate device model to determine the layout and routing of the circuit, and then the simulation is performed to improve the wiring network until satisfactory wiring results are obtained. This design mainly simulates and analyzes the reflection, delay and EMI of MCM layout and wiring in the time domain and frequency domain, and achieves better results.

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  • SMD

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