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Signal Integrity Analysis of High Speed ​​DSP Systems

Posted:10:37 AM November 07, 2018 writer: G

The entire DSP data acquisition system consists of three parts: an analog front-end CCD data acquisition board, a CCD control board, and a data processing main control DSP board. The processed data is transmitted to the uplink PC through the USB2.0 interface.

The analog front-end CCD data acquisition board is composed of a CCD scanning device and an analog-to-digital conversion device A/D. The light source is irradiated onto a photosensitive element called a CCD (Charge Coupled Device) to realize photoelectric conversion. Since the opaque areas of the film to be scanned transmit less light, the transparent areas transmit more light, and the CCD device can detect light of different intensities transmitted through different areas of the image. The CCD scanning device scans the film and converts the RGB three-color signals into three analog signals and sends them to the A/D for sampling, and converts them into RGB digital signals for subsequent processing.

The sampling accuracy of the A/D of the analog-to-digital conversion device and the anti-noise processing of the sampled signal all affect the integrity of the acquired signal and directly affect the processing effect of the subsequent processing board. The A/D we use is a 16-bit 15Msps A/D converter that samples the three-color level signal captured by the CCD into a digital signal. There are three input channels, which correspond to the R, G, and B signal outputs of the CCD device. Each channel consists of an input CLAMP, a dual correction sampler CDS, an offset DAC, and a programmable gain amplifier PGA. This combines into an efficient 16-bit A/D converter that meets the accuracy requirements. At the same time, in order to reduce the CCD to couple the external noise to the system when sampling the analog signal, the RGB three-way signal is isolated by the optocoupler device in the circuit design.

The CCD control board is based on CPLD. The CPLD receives the control signal of the DSP, generates a corresponding control bus and a data bus, and controls the CCD acquisition board to perform handshake data transmission with the DSP board. This part works in an asynchronous manner, and the rate can be achieved by a programmable wait period and the device's response signal, which is easy to achieve signal integrity requirements.

Data Processing The main control DSP board is the core of the entire data acquisition system. It is responsible for correcting the digital signals and uploading the image data to the computer via the USB2.0 interface. The system consists of ADSP21161, CPLD EPM7128AE, 16-bit SDRAM, Flash chip AM29F040, USB interface controller CY7C68013, as shown in Figure 3. Since the system works at very high clock frequencies, this part of the signal integrity problem is very important.

The main control DSP board not only has a high-speed part, but also an asynchronous low-speed part, so it is necessary to invade the system. The purpose of segmentation is to focus on protecting the high-speed part. DSP and USB2.0 control chip and SDRAM interface are synchronous high-speed interfaces. The processing of it is the key to ensure signal integrity; the interface with Flash and CPLD adopts asynchronous interface, and the rate can be realized by programmable waiting period and hardware response signal. It is easy to achieve signal integrity requirements.

The high-speed design section requires the signal line to be as short as possible, as close as possible to the DSP device. However, if the signal line of the DSP is directly connected to all peripherals, on the one hand, the driving capability of the DSP may not meet the requirements. On the other hand, due to the sharp increase in the length of the signal wiring, serious signal integrity problems will inevitably occur. . Therefore, the specific treatment in this system is to isolate the high speed device from the asynchronous low speed device. The 74LS245 is used here for data isolation, using different selection logic to separate different types of data. The 74LS244 is used to form address isolation, and the address drive capability of the DSP is also increased. This solution can reduce the transmission distance of high-speed signal lines to achieve signal integrity requirements.

In addition, it solves the problem of impedance matching of signals in the system, preventing signal reflection, crosstalk noise, etc., and one of the basic conditions for the normal operation of the DSP system. The DSP circuit transmission impedance should match the output impedance of the chip I/O pin. Mismatch can cause signal reflections, which can cause logic clutter. The longer the transmission line, the greater the impact. The series resistors are usually sampled to improve the impedance matching of the transmission line, and the signal lead length should be as small as 15 cm. For leads longer than 15 cm, a 33 Ω matching circuit should be connected in series at the drive end (source end) and the destination end to avoid interference due to signal reflection. In engineering practice, we also use a pull-up resistor at the receiving end to improve the system's drive capability. This is due to the fact that the chip's high-level driving capability is poor, and it is compensated by the external voltage.

Finally, the power supply configuration of the DSP system and the conducted interference of the power supply unit are solved. The ADSP21161 we use is the ADSDP SHARC series DSP processor. The requirements for the system power supply are strict, and the power supply jitter range does not exceed 5%. The core voltage of the chip is 2.5V, the I/O port of the chip is powered by 3.3V, and some conventional integrated circuits are powered by 5V. The system's use of multiple voltage supplies undoubtedly increases crosstalk between various voltages. Among them, the analog power supply AVDD is powered by the clock generator PLL of the DSP, which requires a relatively stable power supply, and the ripple interference is relatively small. Because, we use a high-quality filter network combined with magnetic beads and capacitors to filter the power supply AVDD. The magnetic beads and capacitors here have a significant suppression of power supply ripple. In some high-frequency regions, the magnetic beads have a sharp rise in impedance, so that a good attenuation effect can be obtained in a specific frequency region without affecting the signal transmission of the DSP. The filter network should be as close as possible to the chip pins. In order to avoid noise interference, the analog ground wiring is also required to be as thick as possible.

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