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Serial RapidIO Switching Design Practice Tips for Handling Signal Integrity

Posted:12:25 PM October 30, 2018 writer: G

Currently, high-speed serial links between chips have been widely used to improve overall throughput performance. Processors, FPGAs, and digital signal processors can transfer large amounts of data to each other. In addition, the data may have to be sent from the board through the backplane to the switch card, and the switch card can send data to other cards in the chassis or elsewhere in the "system." Support for RapidIO switching enables interconnection between these different components and is widely used to meet the real-time bandwidth requirements of these applications.

High-speed interface design challenges

Signal quality is very important for all aspects of the system. For serial RapidIO, the signal quality is quantified by the size of the received eye diagram. The receiving eye diagram is an infinitely continuous trajectory in which the waveform repeats continuously with the previous trajectory. The larger the eye diagram is, the better the signal quality will be.

Signal quality can be affected in many ways: noise or other clutter in the signal path, poor signal path wiring, conduction or radiation from external sources, and noise generated by the system itself. All of the above factors combine to cause the receiving eye to shrink. In addition to board-level issues, signal integrity can also be affected by the source (transmission) and destination (receiver) of the connection. Therefore, the source and destination IC characteristics should be considered in the overall system level signal integrity.

Board level design considerations

1. Power input to the board, output and distribution of the local regulator

2. Clock generation and distribution

3. Decoupling

4. PCB base material

5. Interchip connection

6. Inter-board connection and backplane connection

7. Board stacking and impedance control

8. Inter-rack connectors, cables and connectors

Most design best practices for lower frequency board designs need to be modified when operating at frequencies above 300MHz. Consideration must be given to factors that occur when the wavelength is comparable to the board size. This applies not only to the wavelength of the fundamental frequency, but also to the Fourier (frequency domain) component that makes up the complete waveform.

FR4 materials can still be successfully used as the base material for circuit boards, but at higher frequencies, not only the dielectric constant of the material but also the loss factor must be considered. The design of the vias has also become very important because the impedance of the unused tube length (which can be neglected at lower frequencies) will not match the impedance of the thicker board and backplane. It is best to perform post-design simulations to draw attention to wiring that is less than ideal for signal integrity and to indicate crosstalk areas.

The specific challenges in signal integrity on the board are due to the presence of high-speed processor bus and high-speed memory interfaces, clock generation and clock noise, and various board noise sources, typically including: single-ended parallel bus, power distribution, and impedance. Match, ground bounce, crosstalk, and clock generation.

Designers can take many design guidelines to control the effects of noise. Often, good design practices can help board designers control the signal noise generated by board-level communications, including limiting external noise sources and addressing the noise of the device itself.

First, all designs should use the correct trace width, spacing, and topology to ensure that the impedance of each trace matches its transfer device. Impedance mismatch can affect the quality of the leading and trailing edges, stable delay time, crosstalk, and EMI.

It must be ensured that there is sufficient channel spacing between the sync signal groups, the channel length must be limited and the offset between the differential pair signals should be minimized. The number of wiring layer transitions should be minimized during routing to limit parasitic effects. The cost of vias in unnecessary inductors and stray capacitance is very high and should be minimized. In addition to BGA pads, up to two vias are typically allowed per channel.

Thorough verification of signal integrity is critical. Using estimated parasitics, pre-design analysis provides the data needed to understand design performance, but accurate post-design parasitics provide the details needed to discover potential signal integrity issues. With this approach, a circuit netlist can be created to simulate and record the results.

If the channel and signal path are as short as possible, shielded by grounding or physically isolated, and careful to avoid impedance mismatch or any configuration that causes resonance, good signal integrity can be obtained.

Select Serial RapidIO Switch Chip for High Signal Integrity

How do designers choose serial RapidIO switching? Just as good design practices can help board designers control the signal noise generated by board-level communications, hardware designers need to actively consider clock generation characteristics, transmit pre-emphasis and receiver equalization, optimize packaging techniques, and effectively globular mapping. Asynchronously designed serial RapidIO switches ensure high signal integrity at the system level. Obviously, when choosing a serial interface, the chip chosen by the designer must not only have the proper function, but also must be a switch chip designed to solve high-speed signal problems.

Summary of this article

From the above analysis, it can be found that if the basic design rules are well known, the application of high frequency interconnections (such as serial RapidIO) in the system can avoid any traditional problems related to poor signal integrity, such as noise, transient effects, crosstalk or jitter, etc.

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