After years of growing parallel bus widths, there is another trend in the opposite direction of bus technology, where narrow serial buses begin to replace wide parallel structures. For example, a 128-bit parallel connection will become a four-wire serial bus. Of course, these fewer physical connections still have to transmit the same data as the wide parallel bus, and even more.
The serial bus generally transfers data in a packed form, and the packet transmission is done through physical layer technology and then implemented on the protocol layer.
Serial bus serial benefits are many, such as packaged data is more adaptable (character length can vary dynamically with system requirements), higher reliability, and built-in error detection and correction. In addition, the fewer signal lines, the fewer paths that need to be laid out, and the fewer bends, vias, and endpoints. In short, the serial bus is fast, easy to operate, and highly reliable, just in keeping with the system's need for higher bandwidth and performance.
In addition to these advantages, the serial bus presents some new challenges to system designers.
Designers must consider very high speeds and new dynamic performance when planning the application of these signals and troubleshooting. The selected test tools must be consistent with fast signals with complex protocols such as RapidIO, PCI-Express, and Hypertransport. Wait for a lot of information to be transmitted.
In addition to keeping up with speed, designers are now dealing with "design integration" of hardware, software and firmware. Embedded software, digital logic, analog circuits and printed circuit boards are no longer separate development units. At the same time, consider analysis to effectively solve more and more signal integrity problems. The data content is divided into different packets by time. The cause of the error may be in the application software itself, or it may be a packet protocol, digital logic or bus timing error.
Pure logic design is not enough. Today's system speed has some other effects that must be understood and considered, but many engineers are not used to thinking like this. In the past, digital designers focused on timing issues between signals. Now, we must consider the signal parameters inside and between the devices. These factors combine to cause a significant increase in signal integrity problems, making troubleshooting work. More difficult than before.
The first line of defense for most digital troubleshooting tasks is the logic analyzer, which allows users to store, trigger, and view digital signals in a variety of formats. The probe connected to the system under test sends the data to a number of different channels of the logic analyzer, and then displays the digital bursts and their associated locations in time by the logic analyzer. The status display format observes the data at the timing determined by the circuit clock signal under test. These results can be further illustrated by means of a disassembler and processor software support package, which can represent advanced instructions in a low-level binary manner.
The logic analyzer has a high channel count, deep memory memory, and advanced triggering to obtain digital information from numerous test points and then continuously display information. The resulting timing diagram is clear and easy to understand, easy to compare with pre-designed data, and determines if the system is working properly at the binary level. These timing diagrams are often the starting point for finding problems that jeopardize signal integrity.
But not every logic analyzer is suitable for signal integrity analysis at modern fast serial bus data rates, it must have some advanced features to meet these requirements, including 8GHz acquisition rate (125ps timing resolution), thousands of Configure channels, storage depths above 256M, high-density compression probes without adapters, and more. In addition to these hardware features, today's high-end logic analyzers come with advanced analysis software packages to help users get high-level code from the acquired binary data and explain it. The latter feature is not available when analyzing information to package serial data. Lack of.
Many numerical problems can be better understood by observing the analog waveform display of the defective digital signal, although the problem occurs in the form of an error in the digital pulse position, but the cause may be related to the analog characteristics. These analog changes become digital faults when a small amplitude signal is converted to an incorrect logic state or when a rise time is slow and a pulse timing transition occurs.
A digital storage oscilloscope (DSO) captures the detail portion of each digital cycle up to a pulse or edge. DSOs can catch one-off events that are not available with other tools, especially in high-speed signal environments where DSO is the best tool for discovering issues such as transients and jitter.
As with logic analyzers, oscilloscopes must meet stringent performance specifications if they are to be used for signal integrity measurements. Today's advanced oscilloscopes have bandwidths up to 6 GHz on multiple acquisition channels at full sample rate and record lengths up to 32M. They also feature low-capacity mobile probes and a variety of automation, analysis and compliance measurement software to meet your requirements.
Logic Analyzers and DSOs are two powerful signal integrity troubleshooting tools that, along with the latest advances in integration technology, combine these two tools to enhance their functionality.
Both digital information and analog waveforms are time-aligned so that digital events can be checked in an analog manner, such as burst errors in digital waveforms. Signal rising edge anomalies can be seen on the oscilloscope waveform. This analog signal anomaly may be Measure the cause or result of the logic error of the circuit. In either case, finding internal simulation features helps designers track problems faster.
Signal integrity problems often occur in the form of intermittent digital faults. For example, jitter-related errors may occur only once in millions of cycles. Such errors are difficult to replicate and are therefore difficult to find. Signal integrity testing can reveal the initial problems with board layout. For example, a badly terminated bus can cause reflections and signal distortions that affect digital performance, and then track the digital errors until the deformed analog signal passes through the integrated logic analyzer/ The oscilloscope proves that the digital error is indeed related to the layout, and has nothing to do with logic.