* Layout DFM requirements
1. The preferred routing has been determined and all devices have been placed on the board.
2. The origin of the coordinates is the intersection of the left and lower extension lines of the board frame, or the lower left pad of the lower left socket.
3. The actual PCB size, positioning device position, etc. are consistent with the process structure element map, and the device layout in the area where the device height is required is full.
* Meet the structural element map requirements.
4. The DIP switch, reset device, indicator light, etc. are in the right position, and the handle bar does not interfere with the surrounding devices.
5. The outer frame of the board has a smooth curvature of 197 mils or is designed according to the structural dimensions.
6. Ordinary plates have a 200 mil process edge; the left and right sides of the back plate have a process edge greater than 400 mils, and the upper and lower sides have a process edge greater than 680 mils. The device placement does not conflict with the window opening position.
7. All the additional holes (ICT positioning holes 125mil, handle bar holes, elliptical holes and fiber holder holes) need to be added, and the settings are correct.
8. The wave pitch, device orientation, device pitch, device library, etc. of the wave soldering process take into account the requirements of wave soldering.
9. Device layout spacing meets assembly requirements: surface mount devices greater than 20 mils, ICs greater than 80 mils, and BGAs greater than 200 mils.
10. The crimping member is larger than 120 mils in the component surface area higher than its component, and there is no device in the penetration area of the soldering surface crimping member.
11. There are no short devices between the high devices, and no chip devices and short and small interposer devices are placed within 5 mm between devices with a height greater than 10 mm.
12. Polar devices have a polar silkscreen logo. The same type of polar insert components X, Y are the same in their respective directions.
13. All devices are clearly identified, and no P*, REF, etc. are not clearly identified.
14. The surface containing the patch device has 3 positioning cursors and is placed in an "L" shape. Position the center of the cursor at a distance of more than 240 mils from the edge of the board.
15. If you need to do the panel processing, the layout is easy to imposition, which is convenient for PCB processing and assembly.
16. Notched plate edges (shaped edges) should be filled by means of milling slots and stamp holes. The stamp holes are non-metallic, usually 40 mils in diameter and 16 mils apart.
17. The test points for debugging have been added to the schematic and the position in the layout is appropriate.
* Thermal design requirements for layout
18. The heating element and the exposed device of the case are not in close proximity to the wire and the thermal element, and other devices should be kept away.
19. Radiator placement Considering convection problems, there is no high component interference in the projection area of the heat sink, and the surface is marked with silk screen on the mounting surface.
20. The layout takes into account the reasonable smoothness of the heat dissipation channel.
21. The electrolytic capacitor is properly removed from the high heat device.
22. Consider the heat dissipation of high power devices and devices under the gusset.
* Layout signal integrity requirements
23. The start match is close to the originating device and the termination matches the receiver device.
24. Decoupling capacitors are placed close to the relevant device
25. Crystals, crystal oscillators, and clock drive chips are placed close to the relevant device.
26. High speed and low speed, digital and analog are arranged separately by module.
27. Determine the topology of the bus based on analytical simulation results or existing experience to ensure that system requirements are met.
28. If the design is changed, the signal integrity problem reflected in the test report is simulated and a solution is given.
29. The timing of the synchronous clock bus system is designed to meet timing requirements.
* EMC requirements
30. Inductive devices such as inductors, relays, and transformers that are susceptible to magnetic field coupling are not placed close to each other. When there are multiple inductor coils, the direction is vertical and not coupled.
31. In order to avoid electromagnetic interference between the single-plate soldering surface device and the adjacent single-board, the soldering surface of the single-board is not placed with sensitive components and strong radiating devices.
32. The interface device is placed close to the edge of the board. Appropriate EMC protection measures (such as measures with shielded casing and power grounding) have been taken to improve the EMC capability of the design.
33. The protection circuit is placed near the interface circuit and follows the pre-protection filtering principle.
34. Devices with large or very sensitive transmit power (such as crystals, crystals, etc.) are more than 500 mils from the shield and shield case.
35. Place a 0.1uF capacitor near the reset line of the reset switch to reset the device and reset the signal away from other strong interfering devices and signals.
* Layer setting and power ground segmentation requirements
36. The vertical routing rules must be defined when the two signal layers are directly adjacent.
37. The main power plane is as close as possible to its corresponding ground plane, and the power plane satisfies the 20H rule.
38. Each wiring layer has a complete reference plane.
39. Multilayer laminate and core material (CORE) are symmetrical to prevent uneven distribution of copper density and warpage due to asymmetry of medium thickness.
40. The thickness of the plate does not exceed 4.5mm. For the thickness of the plate greater than 2.5mm (the backing plate is larger than 3mm), the technician must confirm that the PCB processing, assembly and equipment have no problem. The thickness of the PC card is 1.6mm.
41. The thickness of the via is greater than 10:1 and is confirmed by the PCB manufacturer.
42. The power supply and ground of the optical module are separated from other power sources and ground to reduce interference.
43. The power and ground handling of critical components meets the requirements.
44. When there is impedance control requirement, the layer setting parameters meet the requirements.
* Power module requirements
45. The layout of the power supply section ensures smooth and non-intersecting of the input and output lines.
46. When the board supplies power to the gusset, the corresponding filter circuit is placed near the power outlet of the board and the power inlet of the gusset.
* Other requirements
47. The layout takes into account the smoothness of the overall alignment and the main data flow is reasonable.
48. Adjust the pin assignment of devices such as exclusion, FPGA, EPLD, and bus driver based on the layout results to optimize the routing.
49. The layout takes into account the appropriate increase in the space at the dense lines to avoid situations where it is not possible.
50. If special materials, special devices (such as 0.5mm BGA, etc.) and special processes are adopted, the delivery deadline and processability have been fully considered, and confirmed by PCB manufacturers and technicians.
51. The pin correspondence of the gusset connector has been confirmed to prevent the direction and orientation of the gusset connector from being reversed.
52. If there is an ICT test requirement, the layout is taken into account with the feasibility of adding ICT test points to avoid the difficulty of adding test points during the wiring phase.
53. When a high-speed optical module is included, the layout preferentially considers the optical port transceiver circuit.
54. After the layout is completed, a 1:1 assembly drawing is provided for the projecter to check whether the device package selection is correct against the device entity.
55. The window has been considered to be retracted in the window and a suitable prohibited wiring area has been set.