The generated netlist can be manually edited based on the schematic, and the automatic routing can be performed after the check is passed. Plates that are automatically laid out and routed with board software are not ideal. The error in the network table may be that the component package in the schematic is not specified; it may also be that the library in the distribution board does not contain all the component packages in the specified schematic. If it is a single panel, do not use automatic wiring. The double panel can be used for automatic wiring. It is also possible to manually and other automatic signals on the power supply and important signal lines.
88. PCB and PCB connection, usually by inserting gold or silver "finger" to achieve, if the "finger" and socket contact bad how to do?
If it is a cleaning problem, clean it with a special electrical contact cleaner or use a writing eraser to clean the PCB. Also consider whether 1, whether the gold finger is too thin, whether the pad is not consistent with the socket; 2. if the socket is in loose perfume or impurities; 3. whether the quality of the socket is reliable.
89. How to use power PCB to set the 4 layers?
The layer definition can be set to 1: no plane + component (top route) 2: cam plane or split/mixed (GND) 3: cam plane or split/mixed (power) 4: no plane + component (if the single plane element can be Defined as no plane+route. Note: The cam plane generates power and the ground plane is a negative, and cannot be routed in this layer. Split/mixed generates a positive film, and this layer can be used as a power source or ground, and can also be walked in this layer. Lines (which are recommended to be routed between the power plane and the ground plane, as this will destroy the integrity of the layer and may cause EMI problems). Add the power network (such as 3.3V, 5V, etc.) from the left-hand list to the right-hand list in the layer 2 assignment, thus completing the layer definition
90. What is the meaning of each layer in PCB?
Mechanical layer: defines the appearance of the entire PCB board, that is, the overall structure of the PCB board. Keepoutlayer Disables the wiring layer: Defines the copper side of the cloth's electrical characteristics. That is to say, after defining the disabling of the wiring layer, in the course of the subsequent cloth-laying, the line having the electrical characteristics may not exceed the boundary of the disabling wiring layer. Topoverlay Top Bottom Screen & Bottomoverlay bottom screen: The silkscreen characters defining the top and bottom are the component numbers and characters commonly seen on the PCB. Toppaste Top Pad Layer & Bottompaste: Bottom Pad Layer: refers to the exposed copper we can see. Topsolder Top Solder Mask & Bottomsolder Bottom Solder Mask: Contrary to to paste and bottom paste, it is a layer that is covered with green oil. Drill guide Via Guide Layer: Drilldrawing Via Hole Drilling Layer: Multiplayer Multilayer: refers to all layers of the PCB board.
91. In high-speed PCBs, VIA can reduce the large return path, but some of them say that they don't want to bend and they don't want to play VIA. How should they choose?
Analyzing the return path of an RF circuit is not the same as the signal return in high-speed digital circuits. First of all, the two have in common, all are distributed parameter circuits, and they are the characteristics of the circuit using the maxwell equation. However, the RF circuit is an analog circuit, and there are voltages in the circuit V=V(t). The current I=I(t) needs to be controlled and the digital circuit only pays attention to the change of the signal voltage V=V(t). Therefore, in RF wiring, in addition to considering signal reflow, it is also necessary to consider the influence of the wiring on the current. That is, the bent wiring and vias have no influence on the signal current. In addition, most RF boards are single-sided or double-sided PCBs, and do not have a complete planar layer. The return path is distributed around the signal and on the power supply. The simulation needs to use 3D field extraction tools for analysis. The backflow of the vias requires specific analysis; high-speed digital circuit analysis generally only deals with multi-layer PCBs with complete planar layers. Using 2D field extraction analysis, only the signal backflow in adjacent planes is considered. The vias only serve as a lumped parameter R -L-C processing.
92. In the design of PCB board, there are the following two stacking scheme: Stack 1 "signal" to "signal" power supply +1.5V "signal" power +2.5V "signal" power +1.25V "power +1.2V " Signal "Power Supply +3.3V" Signal "Power Supply +1.8V" Signal "Ground" Signal Stack 2 "Signal" Ground "Signal Power" +1.5V "Signal" Ground Signal "Power Supply +1.25V +1.8V" Power Supply +2 .5V +1.2V Signal Ground Signal + Power Supply +3.3V Signal Ground Signal Which stacking order is preferable? For stack 2, will the two split power planes in the middle affect the adjacent signal layers? The two signal layers already have a ground plane to signal as a return path.
It should be said that both cascades have their own advantages. The first one guarantees the integrity of the plane layer, and the second increases the number of layers, which effectively reduces the impedance of the power plane and is good for suppressing system EMI. In theory, the power plane and the ground plane are equivalent to the AC signal. However, in practice, the ground plane has a better AC impedance than the power plane, and the signal preferably has a plane as the return plane. However, due to the effect of layer thickness, for example, the thickness of the medium between the signal and the power layer is less than the thickness of the medium between the layers, the signals in the second layer are also incomplete at the power source separation.
93. When the signal is divided across the power supply, does it mean that the AC impedance of the power plane is large for the signal? At this point, if the signal layer still has a ground plane adjacent to it, will the signal select the ground plane as the return path even if the dielectric thickness between the signal and power plane layers is less than the dielectric thickness between the ground plane and the ground plane?
Yes, this is true. According to the impedance calculation formula, Z=squa(L/C). At the separation, C becomes smaller and Z increases. Of course here, the signal is also adjacent to the formation, C is relatively large, Z is small, and the signal is preferentially returned from the complete ground plane. However, it is inevitable that there will be impedance discontinuities at the separation.
94. Using protel 99se software design, the processor is 89C51, crystal 12MHZ system also has a 40KHZ ultrasonic signal and 800hz audio signal, at this time how to design the PCB to provide high anti-interference ability? For 89C51 and other microcontrollers How much signal can affect the normal operation of the 89C51? In addition to widening the distance between the two, there are no other skills to improve the system's ability to resist interference?
The PCB design provides a high anti-jamming capability. Of course, it is necessary to minimize the signal change edge rate of the interference source signal. The specific high-frequency signal depends on the level of the interference signal and how long the PCB layout is. In addition to spacing, the problem of reflection and overshoot of interfering signals by matching or topology can also reduce signal interference.
95. What effect does the pad have on high-speed signals?
A good question. The impact of the pad on the high-speed signal has an effect similar to that of the device package on the device. After a detailed analysis, the signal comes out of the IC and passes through the bond wires, pins, package housings, pads, and solder to the transmission line. All the joints in the process will affect the signal quality. However, in the actual analysis, it is difficult to give the specific parameters of the pad, solder, and pin. Therefore, they are generally summarized with the encapsulation parameters in the IBIS model. Of course, such analysis can be received at a lower frequency, and it is not accurate enough for higher-frequency signal simulation with higher accuracy. The current trend is to use the IBIS V-I and V-T curves to describe the buffer characteristics and the SPICE model to describe the package parameters. Of course, there are also signal integrity problems in IC design, and the influence of these factors on signal quality is also considered in package selection and pin assignment.
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