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Method for solving signal integrity problems in ASIC chip design

Posted:05:56 PM July 12, 2018 writer: G

Reliability and manufacturability

The trend in the industry today is that the number of chip gates continues to increase, and the performance of the chip also increases as the feature size shrinks. Moore's theorem shows that the clock speed and the number of circuit gates double every 18 months. In order to maintain the safe working limits in the design, the continuous fineness of the process technology requires a corresponding reduction in the supply voltage. At the same time, the power consumption on each circuit gate is also reduced. The reduction in power supply voltage and the reduction in power consumption on each gate are always accompanied by an increase in the number of gates and an increase in the clock frequency.

For example, in a new generation of process technology, a high-performance processor plans to consume 300W with a 1.8V supply voltage. The average size of ASIC chips will reach 34 million gates and the clock frequency will exceed 450 MHz. The next-generation ASIC chip's supply current will be much higher than existing chips. Compared to the same ASIC design in the 0.35um process, the 0.18um ASIC chip consumes more than 6 times the power and the current strength exceeds 10 times.

An increase in power and current can result in the migration of electrons. Metal-to-metal migration occurs on high-power unidirectional networks due to current flow, especially when current flows through signal line bends or into tight spaces. The self-heating phenomenon at the high resistance on the signal line through which the bidirectional current flows also causes migration problems.

The reduction in chip feature size also requires a corresponding reduction in the size of the gate oxide region. A high potential region in the switching circuit can capture electrons in the gate oxide region. The destruction of the oxidation zone and the resulting change in the corresponding gate threshold is a cumulative process that is related to the switching frequency and depends on the rate of signal conversion.

If the switching frequency is maintained at a safe limit, the normal operating life of the device can be predicted. However, the challenge is to develop a completely new approach to controlling the thermoelectric effect of the frequency or slew rate above the safety limit. The user must fully characterize the effects of these effects. First, they must simulate the transient conditions of the internal standard cell circuits. They then have to compare the simulation results under current density limits with the actual silicon structure test results. Finally, they need to create a device model that accurately reflects the actual device and process technology.

Circuit analysis follows a number of different methods, all of which require the calculation of the actual switching frequency. One way to solve the problem is to simulate the exact response of all circuits based on the feature model. Another approach is to develop a probabilistic model to strictly approximate the actual behavior in the silicon structure.

To solve the problems associated with metal migration and hot electron injection, the first method is to insert buffers on long lines, which usually have higher current and faster signal switching speed. It should be emphasized that if the buffer speed is just below the driver, this method can reduce the load capacitance on the signal line and reduce the signal conversion rate. Another possible solution is to change the driver and receiver unit.

Antenna effect and noise

A plasma etch process on the metal layer forces the charge to build up on the gate of the IC. The smaller and smaller gate area ratio and the increasing ratio of interconnect signal line lengths will result in capacitive partial voltages, which further damage the device, which is a cumulative process. The basic method to minimize this antenna effect is to limit the area of the metal area and the ratio of the perimeter, and to limit the ratio of the area of the gate to the circumference. The use of such rules can reduce the charge accumulation and transfer process.

Another alternative strategy is to use a routing tool that relies on the antenna to compensate for routing rules. This prevents or minimizes the antenna current, but the cost of this approach is that it results in a larger chip area. Another possible method is to connect a long antenna to the diffusion region, and a diffusion resistor to transfer the charge to other regions (such as a substrate). Finally, the insertion buffer can also reduce the length of the line and insert a diffusion resistor (P-type or N-type output transistor channel) as a resistive path to the power supply or ground.

The increase in power consumption and supply current can also cause other problems. A large current causes a voltage drop across the power line, which causes an IR drop when current flows through the non-zero-resistance power supply network, thereby reducing the voltage reaching the gate. The method of reducing the resistance on the power supply network is constrained by chip area and wiring blockage. Extracting and analyzing during the physical verification phase requires a complex, full-chip simulation and analysis process that includes simulation and analysis of transient processes, inductance, and capacitive effects.

However, after the placement and routing is completed, there is little or no possibility to solve the above problem, and the situation is even worse. The best way to solve power consumption problems is to carefully study the design planning and implementation strategies in the early stages of design and even in the RTL design phase. RTL's highly accurate power analysis must be tied to logical and physical implementations to ensure the quality of the final design.

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