Blog >> Blog Details Page

# How to quickly solve the signal integrity problem of high speed systems

Posted:03:42 PM November 05, 2018 writer: G

Signal routing was previously seen as a simple concept, and there is no difference between a video signal, a voice signal, or a data signal from a wiring perspective. So in the past few people have been concerned about signal routing problems. However, the situation has changed completely now. The video signal transmission speed has reached 3.3Gbps per channel, and the data signal is far more than 5Gbps per channel. High-speed serial standards like PCI Express, XAUI, SATA, TMDS, and Display Port require design teams and engineers to consider not only signal integrity issues, but also how they affect system performance and reliability.

In order to master this knowledge, engineers must first understand what factors affect signal integrity in the system. Signal integrity loss in the system can be observed by increasing signal jitter. The total jitter of the system is mainly composed of two types of jitter, namely random jitter and deterministic jitter. Random jitter is infinite and essentially obeys a Gaussian distribution, while deterministic jitter is finite and predictable. In 90% of systems, deterministic jitter is a major signal integrity issue that design engineers must address.

Deterministic jitter includes inter-symbol interference (ISI), duty cycle distortion, and periodic jitter, which are caused by bandwidth limitations, clock cycle asymmetry, and cross-coupling or EMI issues, respectively. Passive devices such as connectors, PCB traces, long cables, and other passive components placed along traces are the primary sources of deterministic jitter.

The higher the signal frequency, the greater the attenuation, which can cause power level mismatch in the specified data stream, which in turn causes ISI to occur in the signal. ISI will reduce signal integrity, which is enough to prevent the receiver from correctly extracting any real data from the signal at the receiving end.

The reason for the power level mismatch is that no design engineer can guarantee the transmission of data in the design. The data may be constantly changing (0-10-10-10-1, etc.) or it may be constant (1-1-1-1-1-1, etc.). Obviously, the duty cycle of the above six change bits is six times smaller than the duty cycle of six "1" constant data streams. Since the duty cycle is 6 times smaller, the signal frequency is 6 times higher. If the data stream contains both types, the receiver signal will have a very different power level, because the higher the frequency, the greater the attenuation.

Solve the power mismatch problem

The standard for most high-speed signals is to minimize the number of consecutive bits that are unchanged, such as 8B/10B encoding. This coding scheme ensures that the data stream does not have more than 4 consecutive bits. However, there is still a possibility that 4 times of high power is present in the signal at the receiving end.

To compensate for power level mismatch to reduce ISI, designers can use equalization or de-emphasis techniques. The equalization technique will boost the power of all high-speed bits so that the high-speed bits in the received signal have the same power level as the low-speed bits, thereby reducing the power level mismatch.

De-emphasis is the opposite of equilibrium, but has the same goal: to minimize power level mismatch. It is done by reducing the power of the low speed bits, while equalization is to increase the power of the high speed bits. Therefore, de-emphasis can only be applied to the transmitted bits, and equalization can only be applied to the received bits.

This is not the only way to eliminate deterministic jitter, but users are most likely to need some type of transmitter jitter canceller, such as the de-emphasis described above. The true jitter cancellation scheme requires both of these circuits.

Don't let the jitter break your design, because low-cost signal conditioning solutions are available. Equalization and de-emphasis circuits eliminate jitter caused by long FR traces, connectors, and long cables, and you don't have to worry about understanding the details of signal integrity enhancement techniques, let the jitter terminator deal with it.

2367 1 0 1
• PCB
Prototype
• PCB
Assembly
• SMD
Stencil
 Dimensions: (mm) × Quantity: (pcs) 5 5 10 15 20 25 30 40 50 75 100 120 150 200 250 300 350 400 450 500 600 700 800 900 1000 1500 2000 2500 3000 3500 4000 4500 5000 5500 6000 6500 7000 7500 8000 9000 10000 Other Quantities:(quantity*length*width is greater than 10㎡) OK Layers: 1 2 4 6 8 10 12 Thickness: 0.6 mm 0.8 mm 1.0 mm 1.2 mm 1.6 mm 2.0 mm 2.5 mm Quote now