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How to avoid transmission line effects in high speed PCB design?

Posted:10:51 AM September 03, 2018 writer: G

1. Method of suppressing electromagnetic interference

A good solution to signal integrity issues will improve the electromagnetic compatibility (EMC) of the PCB. It is very important to ensure that the PCB board is well grounded. It is a very effective method to use a signal layer with a ground plane for complex designs. In addition, minimizing the density of the outermost signal of the board is also a good way to reduce electromagnetic radiation. This method can be implemented by using the "surface-level" technology "Build-up" design to make the PCB. The surface area layer is realized by adding a thin insulating layer on the common process PCB and a combination of micro holes for penetrating the layers. The resistors and capacitors can be buried under the surface layer, and the trace density per unit area is nearly doubled. Reduce the size of the PCB. The reduction in PCB area has a huge impact on the topology of the trace, which means a reduced current loop, a reduced branch trace length, and electromagnetic radiation is approximately proportional to the area of the current loop; while a small volume feature means a high density lead. A foot package device can be used, which in turn reduces the length of the wire, thereby reducing the current loop and improving electromagnetic compatibility.

2. Strictly control the length of the trace of the critical network cable

If there are high-speed transition edges in the design, you must consider the problem of transmission line effects on the PCB. The fast integrated circuit chip with a very high clock frequency, which is now commonly used, has such a problem. There are some basic principles for solving this problem: if the CMOS or TTL circuit is used for design, the operating frequency is less than 10MHz, and the wiring length should be no more than 7 inches. The working frequency should be no more than 1.5 inches in length at 50MHz. If the operating frequency reaches or exceeds 75MHz, the wiring length should be 1 inch. The maximum wiring length for GaAs chips should be 0.3 inches. If this standard is exceeded, there is a problem with the transmission line.

3. Reasonable planning of the topology of the trace

Another way to solve the transmission line effect is to choose the correct routing path and terminal topology. The topology of the trace refers to the routing sequence and wiring structure of a network cable. When using high-speed logic devices, the fast-changing edge of the signal will be distorted by the branch traces on the signal trunk trace unless the trace branch length is kept short. Typically, PCB traces use two basic topologies, the Daisy Chain routing and the Star distribution.

For daisy-chain wiring, the wiring starts from the driving end and arrives at each receiving end in turn. If a series resistor is used to change the signal characteristics, the position of the series resistor should be close to the drive end. Daisy chain routing works best in controlling the high-order harmonic interference of the traces. However, this type of routing has the lowest rate of routing, and it is not easy to pass 100%. In the actual design, we make the branch length in the daisy chain wiring as short as possible. The safe length value should be: Stub Delay <= Trt *0.1.

For example, the length of the branch in a high speed TTL circuit should be less than 1.5 inches. This topology occupies less wiring space and can be terminated with a single resistor match. However, this routing structure makes the reception of signals at different signal receiving ends asynchronous.

The star topology can effectively avoid the out-of-synchronization of the clock signal, but it is very difficult to manually complete the wiring on a high-density PCB. The use of an autorouter is the best way to complete star routing. Termination resistors are required on each branch. The resistance of the terminating resistor should match the characteristic impedance of the wire. This can be calculated manually or by using a CAD tool to calculate the characteristic impedance value and the terminal matching resistance value.

In the above two examples, a simple terminating resistor is used, and in practice, a more complicated matching terminal can be selected. The first option is the RC matching terminal. RC matching terminals can reduce power consumption, but can only be used when the signal operation is relatively stable. This method is best suited for matching the clock line signals. The disadvantage is that the capacitance in the RC matching terminal can affect the shape and propagation speed of the signal.

The series resistor matching terminal does not generate additional power consumption, but slows down the transmission of the signal. This method is used for bus drive circuits that have little effect on time delay. The series resistor matching terminal also has the advantage of reducing the number of devices used on the board and the connection density.

The last way is to separate the matching terminals, in such a way that the matching elements need to be placed near the receiving end. The advantage is that it does not pull down the signal and can avoid noise very well. Typical for TTL input signals (ACT, HCT, FAST).

In addition, the package type and mounting type of the termination matching resistor must also be considered. Usually SMD surface mount resistors have lower inductance than via components, so SMD package components are preferred. If you choose a normal in-line resistor, there are two installation options: vertical mode and horizontal mode.

One of the mounting pins of the resistor in the vertical mounting mode is short, which reduces the thermal resistance between the resistor and the board, making the heat of the resistor more easily dissipated into the air. However, a longer vertical installation increases the inductance of the resistor. The horizontal mounting method has lower inductance due to lower installation. However, the overheated resistor will drift. In the worst case, the resistor becomes an open circuit, causing the PCB trace termination to fail, which becomes a potential failure factor.

4. Other available technology

To reduce the transient overshoot of the voltage on the integrated circuit chip supply, decoupling capacitors should be added to the integrated circuit chip. This effectively removes the effects of glitches on the power supply and reduces the radiation in the power supply loop on the printed board.

Smooth deburring works best when the decoupling capacitor is directly connected to the power supply leg of the integrated circuit rather than to the power plane. This is why some device sockets have decoupling capacitors, while others require the decoupling capacitor to be sufficiently small from the device.

Any high speed and high power devices should be placed together as much as possible to reduce transient overshoot of the supply voltage.

If there is no power plane, a long power connection will form a loop between the signal and the loop, becoming a source of radiation and an easy-to-sensing circuit.

The case where a trace forms a loop that does not pass through the same network line or other trace is called an open loop. If the loop passes through other traces on the same network line, it forms a closed loop. Antenna effects (line antennas and loop antennas) are formed in both cases.

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