Principle 31: It is recommended to ground the ground on both sides of the clock line. The ground wire is grounded every 3000 mils. Reason: Ensure that the potentials at each point on the ground are equal.
Principle 32: Key signal traces such as clock, bus, and RF lines: Other parallel lines in the same layer should meet the 3W principle. Cause: Avoid crosstalk between signals.
Principle 33: The surface-mount fuses, beads, inductors, and tantalum capacitors used for power supplies with current ≥1A should be no less than two vias connected to the planar layer. Cause: Reduce the equivalent impedance of the via.
Principle 34: The differential signal lines should be in the same layer, equal length, and walking line. Keep the impedance one: no other traces between the differential lines. Reason: Ensure that the common mode impedance of the differential pair is equal, and improve its anti-interference ability.
Principle 35: Critical signal traces must not be routed across the partition (including vias, pad reference plane gaps). Cause: Routing across the partition will result in an increase in the signal loop area.
Principle 36: When the signal line is split across its recirculation plane, it is recommended to use a bridge capacitor approach near the signal split. The capacitor value is 1nF. Reason: When the signal crosses the segmentation, it often leads to an increase in the loop area. The bridge grounding method is artificially set as the signal loop.
Principle 37: Do not have other unrelated signal traces under the filter (filter circuit) on the board. Cause: The distributed capacitance will weaken the filtering effect of the filter.
Principle 38: The input and output signal lines of the filter (filter circuit) cannot be parallel to each other and cross-wired. Cause: Avoid direct noise coupling before and after filtering.
Principle 39: The critical signal line is ≥3H from the reference plane edge (H is the height of the line from the reference plane). Cause: Suppresses the edge radiation effect.
Principle 40: For metal case grounding elements, the copper should be grounded on the top layer of its projection area. Cause: The external capacitance and the immunity are improved by the distributed capacitance between the metal case and the grounded copper.
Principle 41: In a single or double layer board, attention should be paid to the "reduced loop area" design when wiring. Cause: The smaller the loop area, the smaller the external radiation of the loop, and the stronger the anti-interference ability.
Principle 42: When changing the signal line (especially the key signal line), the via should be designed near the layered via. Cause: The signal loop area can be reduced.
Principle 43: Clock line, bus, RF line, etc.: The strong radiated signal line is away from the outgoing signal line of the interface. Reason: Avoid interference on the strong radiation signal line coupled to the outgoing signal line and radiate outward.
Principle 44: Sensitive signal lines such as reset signal lines, chip select signal lines, system control signals, etc. are far away from the interface outgoing signal lines. Cause: The outgoing signal line of the interface often brings in external interference. When it is coupled to the sensitive signal line, it will cause the system to malfunction.
Principle 45: In single-panel and dual-panel, the trace of the filter capacitor should be filtered by the filter capacitor before the device pin. Cause: The power supply voltage is filtered first and then the IC is powered, and the noise that the IC feeds back to the power supply is also filtered out by the capacitor.
Principle 46: In a single panel or dual panel, if the power cable is very long, add a decoupling capacitor to the ground every 3000 mils. The capacitance is 10uF + 1000pF. Cause: The high frequency noise on the power line is filtered out.
Principle 47: The ground and power cables of the filter capacitor should be as thick and short as possible. Cause: The equivalent series inductance will reduce the resonant frequency of the capacitor and weaken its high frequency filtering effect. Differential mode current and common mode current:
Differential mode current and common mode current:
Radiation produces: Current causes radiation, not voltage, static charge creates an electrostatic field, and constant current produces a magnetic field that produces both an electric field and a magnetic field. Common mode current and differential mode current exist in any circuit. Differential mode signals carry data or useful signals. Common mode signals are the negative effects of differential mode.
Differential mode current: equal in size and opposite in direction (phase). The differential mode current is converted to a common mode current due to the distributed capacitance, inductance, and signal trace impedance of the trace being discontinuous, and the signal return path flowing through an unexpected path.
Common mode current: The sizes are not necessarily equal, and the direction (phase) is the same. The external interference of the equipment is mostly common mode, and differential mode interference also exists, but the common mode interference intensity is often several orders of magnitude larger than the differential mode strength. External interference is mostly dominated by common mode interference. Common mode interference itself generally does not cause harm to the equipment. However, if common mode interference is converted to differential mode interference, it is serious because the useful signals are differential mode signals. The magnetic field of the differential mode current is mainly concentrated in the loop area formed by the differential mode current, and the magnetic lines of force cancel each other outside the loop area; the magnetic field of the common mode current is outside the loop area, and the common mode current generates the same magnetic field direction. Many of the EMC designs for PCBs follow the above theory.
The ways to suppress interference on the PCB are:
Reduce the area of the differential mode signal loop
Reduce high frequency noise reflow (filtering, isolation and matching)
Reduce common mode voltage (ground design)