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High Speed ​​PCB Design Rules Summary and Analysis (2)
Posted:05:21 PM May 29, 2018 writer: G

Reasons: Similar to single board interfaces and other places are the most easily disturbed by external interference (such as static electricity), and sensitive circuits such as reset circuits and watchdog circuits can easily cause system misoperation.

26. Filter capacitors for the IC should be placed as close as possible to the power supply pins of the chip.

Reason: The closer the capacitor is to the pin, the smaller the area of the high-frequency loop, and thus the smaller the radiation.

27. For the beginning series matching resistor, close to its signal output terminal.

Reasons: The design of the series termination resistor at the beginning is to add the impedance of the output impedance of the chip output and the series resistor equal to the characteristic impedance of the trace. The matching resistor is placed at the end and cannot satisfy the above equation.

28. PCB traces can not have a right angle or acute angle alignment.

Reasons: A right-angled trace leads to a discontinuity in the impedance, which causes the signal to emit, causing ringing or overshoot, resulting in strong EMI radiation.

29. As far as possible to avoid the adjacent wiring layer layer settings, can not be avoided, try to make the two wiring layers in the vertical or parallel traces are less than 1000mil.

Reasons: Reduce crosstalk between parallel traces.

30. If the board has an internal signal routing layer, key signal lines such as clocks are placed on the inner layer (preferably the preferred routing layer is preferred).

Reasons: Placing key signals in the internal routing layer can provide shielding.

31. The clock line on both sides of the proposed package ground wire, package ground wire every 3000mil hit ground vias.

Reason: Ensure that the potentials of all points on the package ground are equal.

32. Clock signal, bus line, radio frequency line and other key signal traces: Other parallel traces in the same layer shall meet the 3W principle.

Reasons: Avoid crosstalk between signals.

33. Surface-mount fuses, beads, inductors, and tantalum capacitors used for currents ≥1A should not be less than two vias connected to the plane plane.

Reasons:  Reduce the equivalent impedance of the via.

34. Differential signal lines should be the same layer, the same length, and parallel lines, to maintain the impedance of a: cause, no other traces between the differential lines.

Reasons: Ensure that the differential line pairs have the same common-mode impedance and improve their anti-jamming capability.

35. The critical signal traces must not be routed across the partitions (including vias and pad-induced reference plane gaps).

Reasons: Crossing the partitions leads to an increase in the signal loop area.

36. When the signal line is unavoidable across its reflow plane, it is recommended to use bridging capacitors near the signal cross-section. The value of the capacitor is 1nF.

Reasons:  When the signal is divided, it often leads to an increase in the loop area. The use of a bridging method is artificially designed for the signal loop. .

37. There should be no other unrelated signal traces under the filter (filter circuit) on the board.

Reason: The distributed capacitance will weaken the filtering effect of the filter.

38. Filter (filter circuit) input and output signal lines can not be parallel to each other, cross-line.

Reasons: Avoid direct noise coupling before and after filtering.

39. The critical signal line from the reference plane edge ≥ 3H (H is the height of the line from the reference plane).

Reasons: Edge radiation effects are suppressed.

40. For grounded components in metal enclosures, ground the copper skin on the top of its projection area.

Reasons: The external radiation and noise immunity are suppressed by the distributed capacitance between the metal case and the grounded copper skin.

41. In single-layer boards or double-layer boards, attention should be paid to the "minimum loop area" design when wiring.

Reasons: The smaller the loop area, the smaller the loop external radiation, and the stronger the anti-interference ability.

42. When the signal line (especially the key signal line) is changed, the via hole should be designed in the vicinity of the replacement layer via hole.

Reasons: The signal loop area can be reduced.

43. Clock line, bus, radio frequency line, etc.: strong radiation signal line away from the interface outside the signal line.

Reasons: The interference on the strong radiation signal line is prevented from being coupled to the outgoing signal line and radiated outward.

44. Sensitive signal lines such as reset signal lines, chip select signal lines, system control signals, etc. are far away from the interface outgoing signal lines.

Reasons: Interface outbound signal lines often carry external interference. When coupled to sensitive signal lines, it can cause system misoperation.

45. In single-sided and double-sided panels, the filter capacitor traces should be filtered by a filter capacitor and then to the device pins.

Reasons: The supply voltage is filtered and then supplied to the IC, and the IC's noise back to the power supply is also filtered out by the capacitor.

46. In a single or dual panel, if the power line is long, decoupling capacitors should be added every 3000mil. The value of the capacitor is 10uF+1000pF.

Reasons: Filter out high-frequency noise on the power line.

47. The filter capacitor ground wire and power supply wire should be as thick and short as possible.

Reasons: Equivalent series inductance reduces the resonant frequency of the capacitor and weakens its high-frequency filtering effect.


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