Design and Implementation of VXI Bus Interface Circuit

VXIbus is an extension of VMEbus in the field of instruments and is a computerized modular automatic instrument system. It relies on effective standardization and modularization to achieve serialization, generalization and interchangeability, and interoperability of VXIbus instruments. Its open architecture and PlugPlay approach fully meet the requirements of information products. It has the advantages of high-speed data transmission, compact structure, flexible configuration, good electromagnetic compatibility, etc. Therefore, the system is very convenient to set up and use, and the application is more and more extensive and has gradually become the preferred bus for high-performance test system integration.

The VXI bus is a fully open modular instrument backplane bus specification for each instrument manufacturer. VXI bus devices are mainly divided into register-based devices, message-based devices, and memory-based devices. Register-based devices currently account for the largest proportion (about 70%) of applications. The VXIbus register base interface circuit mainly includes four parts: bus buffer drive, addressing and decoding circuit, data transfer response state machine, configuration, and operation register set. In addition to the bus buffer driver using the 74ALS245 chip in the four parts, the rest is implemented by FPGA. A piece of FLEX10K chip EPF10K10QC208-3 and a piece of EPROM chip EPC1441P8 are used to design and implement the corresponding software MAX+PLUSII.

1. Bus buffer driver

This section completes the buffered reception or drive of the data lines, address lines, and control lines in the VXI backplane bus to meet the VXI specification signal requirements. For the A16/D16 devices, the buffer drive of the backplane data buses D00 to D15 is implemented. According to the requirements of the VXI bus specification, this part is implemented by two 74LS245s, which are gated by DBEN* (generated by the data transfer response state machine).

2. Addressing and decoding circuits

The address lines include address lines A01 to A31, data strobe lines DS0* and DS1*, and long word lines LWORD*. The control line includes an address strobe line AS* and a read/write signal line WRITE*.

The design of this circuit uses the schematic design of MAX+PLUSII. Designed using existing components in the component library, two 74386 and one 74138 are used.

The function module decodes the address lines A15 to A01 and the address modification lines AM5 to AM0. When the device is addressed, it receives the address information on the address line and the address modification line and compares it with the logical address LA7~LA0 set by the hardware address switch on this module. If the logical value on AM5~AM0 is 29H or 2DH (Because it is an A16/D16 device), the address lines A15, A14 are both 1, and the logic value on A13 ~ A06 is equal to the logical address of the module, the device is addressed strobe (CADDR * is true). Then the result is sent to the next level of decoding control, and the module is in the 16-bit address space register by decoding the addresses A01 to A05.

3. Data transfer response state machine

The data transmission bus is a set of high-speed asynchronous parallel data transmission buses, which is the main component of VMEbus system information exchange. The signal lines of the data transmission bus can be divided into three groups of address lines, data lines, and control lines.

The design of this part uses the text input design of MAX+PLUSII. Because the timing of DTACK* is more complicated, the design is implemented in AHDL language and implemented by the state machine.

The function module configures the control signals in the VXI backplane bus to provide timing and control signals for the standard data transmission cycle (generating the data transmission enable signal DBEN*, the response signal DTACK* required for the bus to complete the data transmission, etc.). During data transmission, the system controller first addresses the module and sets the corresponding address strobe line AS*, data strobe line DS0*, DS1*, and WRITE* signal line that controls the data transmission direction to be valid. Level. When the module detects the address match and the control lines are valid, it drives DTACK* low to confirm to the bus controller that the data has been placed on the data bus (read cycle) or has successfully received the data (write cycle) ).

4. Configuration register

Each VXI bus device has a set of “configuration registers”. The system main controller reads some of the basic configuration information of the VXI bus device by reading the contents of these registers, such as device type, model, manufacturer, and address space (A16, A24). , A32) and the required storage space.

The basic configuration registers of the VXI bus device are identification register, device type register, status register, and control register.

The design of this part of the circuit uses the schematic design of MAX+PLUSII, using the 74541 chip, which creates the functional modules.

The ID, DT, and ST registers are read-only registers, and the control registers are write-only registers. In this design, the VXI bus is mainly used to control the on/off of the batch of switches. Therefore, the data can be controlled by writing data to the channel register to control the on/off state of the relay switch. The status of the relay is also read from the channel register. The data is fine. According to the design requirements of the module, the appropriate content is written in the corresponding data bits, so that the RF switch of the function module can be effectively controlled.