Effective Characteristic Impedance Management for PCB Designs

Table of Contents

1. 1. Characteristic Impedance Value Control Reason
2. 2. Characteristic Impedance Z0 and the Relationship Between the Plate and the Process
3. 3. Characteristic Impedance Control Printed Board Process Control

1. Characteristic Impedance Value Control Reasons

1.1. Reason 1

When an electronic device (computer, communication device) is operated, the signal from the driver (Driver) will reach the receiving device (Receiver) through the PCB transmission line. When the signal is transmitted in the signal line of the printed board, its characteristic impedance value Z₀ must match the "electronic impedance" of the head and tail components, and the "energy" in the signal will be completely transmitted.

1.2. Reason 2

In the event of poor quality of the printed board, when the Z₀ is out of tolerance, the transmitted signal will have problems such as reflection, dissipation, attenuation or delay. In severe cases, the signal will be transmitted and the signal will be crashed.

1.3. Reason 3

Strict selection of plates and control of the production process, Z₀ on the multi-layer board can meet the specifications required by customers. The higher the electronic impedance of the component, the faster the transmission speed will be, and the Z₀ of the PCB will also increase to meet the requirements of the matching component. Z₀ qualified multi-layer boards are considered to be qualified products for high-speed or high-frequency signals.

> Recommend reading: What Factors Affect Characteristic Impedance Precision in High-Speed PCB?

2. Characteristic Impedance Z0 and the Relationship Between the Plate and the Process

The characteristic impedance Z₀ of the microstrip line structure is calculated as:

Z₀ = 87 / √(ε_r + 1.41 ln(5.98H / (0.8W + T)))

Where: ε_r - dielectric constant, H - media thickness, W - wire width, T - wire thickness

2.1. The Characteristic Impedance Z0 is Inversely Proportional to the εr of the Sheet

Z₀ increases as the thickness of the medium increases. Therefore, for the strict high-frequency line of Z₀, strict requirements are imposed on the error of the dielectric thickness of the copper clad laminate substrate. Generally, the thickness of the media must not vary by more than 10%.

2.2. Effect of Medium Thickness on Characteristic Impedance Z0

As the density of the trace increases, the increase in dielectric thickness causes an increase in electromagnetic interference. Therefore, the signal transmission line of high-frequency lines and high-speed digital lines should reduce the thickness of the medium as the density of the conductors increases, so as to eliminate or reduce the problem of noise or crosstalk caused by electromagnetic interference, or to greatly reduce εr. εr substrate.

2.3. Effect of Copper Foil Thickness on Characteristic Impedance Z0

The thinner the thickness of the copper foil, the higher the Z₀ value, but the thickness variation does not contribute much to Z₀.

2.4. Influence of Wire Width on Characteristic Impedance Z0

The smaller the line width W, the larger Z₀; reducing the wire width increases the characteristic impedance.

The change in line width is much more pronounced than the change in line thickness on Z₀.

Z₀ increases rapidly as the line width W becomes narrower. Therefore, to control Z₀, the line width must be strictly controlled. At present, the signal transmission line width W of most high-frequency lines and high-speed digital lines is 0.10 or 0.13 mm. Traditionally, the line width control deviation is ±20%. PCB conductors for conventional electronic products that are not transmission lines (wire length < 1/7 of the signal wavelength) can meet the requirements, but for signal transmission lines with Z₀ control, the PCB conductor width deviation is ±20%, which is no longer sufficient. Because the Z₀ error at this time has exceeded ±10%.

Examples are as follows:

A PCB microstrip line has a width of 100 μm, a line thickness of 20 μm, and a dielectric thickness of 100 μm. Assuming that the finished PCB copper thickness is uniform, the line width varies by ±20%, and can Z₀ meet within ±10%?

Solution: according to the formula

Z₀ = 87 / √(ε_r + 1.41 ln(5.98H / (0.8W + T)))

Substitution: line width W₀ = 100μm, W₁ = 80μm, W₂ = 120μm, line thickness T = 20μm, medium thickness H = 100μm, then:

Z₀₁ / Z₀₂ = 1.20

Therefore, Z₀ is just ±10% and cannot reach <±10%. To achieve a characteristic impedance Z₀ <±10%, the wire width deviation must be further reduced and must be much less than ±20%.

For the same reason, to control Z₀ ≤ 5%, the wire width tolerance must be controlled ≤ ±10%.

3. Characteristic Impedance Control Printed Board Process Control

3.1. Film Production Management, Inspection

Constant temperature and humidity room (21 ± 2 °C, 55 ± 5%), dustproof; line width process compensation.

3.2. The Design of the Puzzle

The edge of the panel should not be too narrow, the plating layer is uniform, the plating is added with a false cathode, and the current is dispersed; Design the panel edge to test the coupon of Z₀.

3.3. Etching

Strict process parameters, reduce side erosion, and conduct the first inspection; Reduce residual copper, copper slag and copper on the line side; Check the line width and control within the required range (±10% or ±0.02mm).

3.4. AOI Inspection

The inner plate must find the wire notch and the notch. For the 2GHZ high-speed signal, even the 0.05mm gap must be scrapped; controlling the inner line width and defects is the key.

3.5. Lamination

Vacuum laminator, reduce the pressure to reduce the flow of glue, try to keep more resin, because the resin affects εr, the resin is stored more, εr will be lower. Control laminate thickness tolerances. Because the plate thickness is not uniform, it indicates that the thickness of the medium changes, which will affect Z₀.

3.6. Choose the Substrate

The plate type is strictly required according to the customer's requirements. The model is wrong, εr is wrong, the board thickness is wrong, the PCB manufacturing process is all right, and it is also scrapped. Because Z₀ is greatly affected by εr.

3.7. Solder Mask

The solder mask of the board surface will reduce the Z₀ value of the signal line by 1~3Ω. In theory, the thickness of the solder mask should not be too thick, and the effect is not very large. The surface of the copper wire is exposed to air (εr =1), so the Z₀ value is measured to be high. However, after the solder mask, the Z₀ value will drop by 1 to 3 Ω, because the εr of the solder resist is 4.0, which is much higher than the air.

3.8. Water Absorption Rate

The finished multi-layer board should avoid water absorption as much as possible, because the water εr = 75, which will bring about a large drop and instability effect on Z₀.