Some of the problems with high-speed circuits are not very serious, while others are catastrophic. For example, signal oscillation caused by the establishing behavior of the signal reflected back and forth on the transmission line may cause false triggering of the device (multiple clocking). Signal overshoot, mainly due to signal reflection, can cause timing errors and can even damage components. After the rise time of the signal drops below 1 ns, crosstalk between signals becomes a very important issue. Crosstalk typically occurs in high-density board designs, while the signal transitions are very fast, and line-to-line coupling is very easy to form crosstalk. When the signal rise time is less than 1 ns, the high-frequency harmonic components in the signal are easily coupled to adjacent signal lines to form crosstalk. Therefore, such a system is prone to problems if there are a large number of high-speed interconnected signal lines in the board. The advent of high-speed devices has caused the rise time of the signal to be less than 0.5 ns, causing more problems in the designed system: stability problems in the power system and electromagnetic interference (EMI) problems. When the frequency of data changes on the data bus is high, the stability of the power system may occur, resulting in large fluctuations and fluctuations in the power plane. Large fluctuations and fluctuations in the reference plane in the system may affect the signals in the design. This type of system design requires careful planning of the power system design and selection of the most reasonable decoupling strategy for the power system. The close integration of the two is the key to ensuring the stability of the power system. Fast signals are also more prone to radiation, so EMI is becoming more and more of a concern for design engineers and an important aspect that must be considered in new designs. Especially today's electronic products must face many of the industry's norms.
Unfortunately, in low-speed system designs, the potential crisis caused by reduced signal rise times is often overlooked by design engineers. This is because design engineers do not want to perform signal integrity analysis and avoid it as much as possible. The real danger is that many boards are sent to processing in the event that signal integrity issues are not known. At the same time, due to the unpredictability of the signal integrity problem itself, the signal integrity problem may not be manifested during the final test of the printed circuit board, and the signal integrity problem when the product is sent to the end user. May appear. The failure of the product at the user site and the diagnosis and resolution of the problem will become very difficult. The real risk is also the higher NRE (one-time engineering cost) costs. Every board product design manufacturer will share all NRE costs over the life of the product. The design iterations caused by unpredictable high-speed signal integrity issues after the board is designed and manufactured will quickly increase the NRE cost.
There is a well-known axiom in the field of electronic product design and production: the product enters the production phase from the design stage, and the cost of repetitive work increases exponentially, and once the product has been distributed to the end user site, the cost of such rework will become higher. . Therefore, any board-level design that can work normally during the design and production process, if it is found that there is a problem after the product is sent to the user's site, the design engineer expects to find and solve the problem in the traditional high-speed design field, and the product development progress. The cost structure will bring greater risks. These costs include not only the huge cost incurred by the large amount of repetitive work directly caused, but also the dissatisfaction and loss of confidence of users. The above questions strongly urge the introduction of a new step in the development cycle of any board-level product to prevent signal integrity problems from sneaking into the production process. For many years, ASIC design engineers have developed a good habit. As part of the contractual agreement, ASIC design engineers must sign the “Sign-Off” design with the ASIC manufacturer to ensure the integrity of the design data. . In the custom chip development process, the cost of NRE investment may be hundreds of thousands of dollars. IC production and processing manufacturers strongly demand that each such design must pass the "golden version" simulator test to protect its own cost and Rights and obligations. In addition, the “Signature Acceptance” step effectively protects and constrains designers and process manufacturers from requiring IC process manufacturers to produce qualified, high-quality device products for their customers, as well as IC design engineers. More standardized, the device is designed to be highly manufacturable. For board design and manufacturing manufacturers, Sign-Off of high-speed circuit design (signal integrity verification before the board is sent to manufacturing) is equally important. As a step in the general design process, using high-speed signal integrity verification test tools for analysis and verification of each board-level design (regardless of the speed of the clock in the design), the design engineer must ensure that the signal integrity issues in the design are The design has been resolved before it is sent to the manufacturing process. As a result, design engineers are confident that the products they design have better quality assurance. Unpredictable signal integrity issues will no longer occur after the designed product is shipped to the end user site. Design engineers will no longer have to worry about whether they have added appropriate design constraints to address signal integrity issues in board-level design, or whether they have done their best to focus on critical high-speed signal line issues during the design process. Sign-Off signal integrity after board layout can eliminate this risk and engineers' concerns.
Which type of emulator can provide the best solution for signal integrity analysis to verify Sign-Off? An ideal simulator can analyze a system consisting of a whole board or multiple boards at the same time, rather than just analyzing individual signal lines on the board. Speed is also a critical factor, and it is important to perform accurate signal integrity analysis within a reasonable time frame. The SPICE-based signal integrity analysis engine has sufficient analysis accuracy, but the analysis takes a long time to build and the analysis runs slower, so this type of tool is not practical.
The “Gold Edition” simulator must also provide an accurate internal model for the transmission line. With the reduction of signal rise time and fall time, the ideal lossless transmission line model adopted by many signal integrity analysis engines has been unable to meet the analysis accuracy requirements. At this time, the transmission line should be modeled as a truly lossy transmission line model, and in order to facilitate the resolution of signal integrity problems, a comprehensive and informative analysis report should be provided, and the specific components or specific interconnection lines can be specified in a convenient and detailed manner. Signal integrity violation. Finally, such tools should also have powerful "What-If" analysis capabilities to help design engineers identify more appropriate system topologies, wired termination schemes, and driver/receiver options.
In addition, such tools must have sufficient capabilities to solve complex problems such as analysis and design of the power plane and electromagnetic radiation, and can reveal the interrelationships between them and find the most appropriate solution through compromise. Last but not least, this type of tool must support the most advanced models, because the final analysis results ultimately depend on the model used in the analysis.
Ideally, design engineers will want to adopt the right strategy when implementing place and route to minimize the problems of high speed. Implementing high-speed design methodology will undoubtedly greatly increase the cost-effectiveness of design products: signal integrity analysis is implemented during the planning phase prior to placement and routing in the product development cycle. The new generation of EDA technology uses constraint-driven placement and routing to help reduce costly design iterations. Innoveda's ePlanner tool, for example, allows design engineers to think about the prototype of a PCB topology before passing the design down to the subsequent layout process. For example, the ePlanner tool provides a graphical design space exploration and interconnected planning and design environment in which design engineers can implement “What-If” analysis to explore high-speed signal strategies and build for downstream routers. Reasonable design rules based on analytical conclusions.
In the long run, the best solution for solving high-speed designs in the future is to perform signal integrity analysis as early as possible in the design cycle and tightly integrate signal integrity analysis with place-and-route. However, as far as the current situation is concerned, the minimum requirement is that the high-speed design of Sign-Off (signal integrity verification and testing performed before the board is sent for fabrication) must be a standard in every board design flow. step.